[coreboot-gerrit] Change in coreboot[master]: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )

Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... 
File src/cpu/intel/socket_mPGA604/Kconfig:

https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... 
PS2, Line 29: 0xffef0000
> any reason why?

You suggested value below 1 << 28, bottom 64 MiB? We want to stay above TOLM but need to avoid some of FWH RW bank registers that extend below ROM size.

I was supposed to put 0xfef00000 here.