Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46499 )
Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ......................................................................
soc/intel/xeon_sp/cpx: Lock down P2SB SBI
This is required for CBnT.
Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/46499 Reviewed-by: Christian Walter christian.walter@9elements.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/p2sb.h 2 files changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3daff13..b7752b2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -11,8 +11,10 @@ #include <soc/chip_common.h> #include <soc/cpu.h> #include <soc/ramstage.h> +#include <soc/p2sb.h> #include <soc/soc_util.h> #include <soc/util.h> +#include <soc/pci_devs.h>
/* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) @@ -63,6 +65,8 @@
static void chip_final(void *data) { + /* Lock SBI */ + pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); p2sb_hide();
set_bios_init_completion(); diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h index 336befe..3bdd453 100644 --- a/src/soc/intel/xeon_sp/include/soc/p2sb.h +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -11,3 +11,6 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0xb0 #define P2SB_SIZE (16 * MiB) + +#define P2SBC 0xe0 +#define SBILOCK (1 << 31)