KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43756 )
Change subject: cast all void *cbmem_top_chipset() function to uintptr_t ......................................................................
cast all void *cbmem_top_chipset() function to uintptr_t
Cast all cbmem_top_chipset to uintptr_t
Change-Id: I12b105a5b49e2bbe2753a75eeff28fed29ee2297 Signed-off-by: root kouamdoux@gmail.com --- M src/acpi/acpi.c M src/arch/x86/cbmem.c M src/cpu/ti/am335x/cbmem.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/acpi/acpi.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 36 files changed, 206 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43756/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 47f03c8..994cf93 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -507,6 +507,59 @@ return mem->length; }
+int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic) +{ + lx2apic->type = 2; + lx2apic->length = sizeof(acpi_srat_lx2apic_t); + lx2apic->proximity_domain = node; + lx2apic->lx2apic_id = x2apic; + lx2apic->flags = (1 << 0); + /* TODO: clock domain: lx2apic->clock_domain */ + lx2apic->resv1 = 0; + lx2apic->resv2 = 0; + + return lx2apic->length; +} + +int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu) +{ + gicc->type = 3; + gicc->length = sizeof(acpi_srat_gicc_t); + gicc->proximity_domain = node; + gicc->processor_id = cpu; + gicc->flags = (1 << 0); + /* TODO: clock domain: gicc->clock_domain */ + + return gicc->length; +} + +int acpi_create_srat_its(acpi_srat_its_t *its, u8 node, u8 cpu) +{ + its->type = 4; + its->length = sizeof(acpi_srat_its_t); + its->proximity_domain = node; + its->resv = 0; + its->its_id = cpu; + + return its->length; +} + +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struct_t *gen, u8 node, u8 cpu) +{ + gen->type = 5; + gen->length = sizeof(acpi_srat_gen_init_struct_t); + gen->resv1 = 0; + /* TODO: Device Handle type: gen->device_hdle_type*/ + + gen->proximity_domain = node; + /* TODO: Device handle for the generic Initiator*/ + + gen->flags = (1 << 0); + gen->resv2 = 0; + + return gen->length; +} + /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 353368a..6b25132 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
#if CONFIG(CBMEM_TOP_BACKUP)
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return (uintptr_t)(restore_top_of_low_cacheable()); }
#endif /* CBMEM_TOP_BACKUP */ diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index 3765874..a5bc1c5 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t) (_dram + (CONFIG_DRAM_SIZE_MB << 20)); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..796356c 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -2,11 +2,12 @@
#include <cbmem.h> #include <fsp/util.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return (uintptr_t)(range_entry_end(&tolum)); } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index cd99899..aa6bfa1 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -235,6 +235,49 @@ u32 resv2[2]; } __packed acpi_srat_mem_t;
+/* SRAT: x2APIC Affinity Structure */ +typedef struct acpi_srat_lx2apic { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (24) */ + u16 resv1; /* Reserved */ + u32 proximity_domain; /* Proximity Domain */ + u32 lx2apic_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ + u32 resv2; +} __packed acpi_srat_lx2apic_t; + +/* SRAT: GICC Affinity Structure*/ +typedef struct acpi_srat_gicc { + u8 type; /* Type (3) */ + u8 length; /* Length in bytes (18) */ + u32 proximity_domain; /* Proximity Domain */ + u32 processor_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ +} __packed acpi_srat_gicc_t; + +/* SRAT: Architecture Specific Affinity Structure */ +typedef struct acpi_srat_its { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (12) */ + u32 proximity_domain; /* Proximity Domain */ + u16 resv; + u32 its_id; /* ITS ID matching a GIC ITS entry in the MADT */ +} __packed acpi_srat_its_t; + +/*SRAT: Generic Initiator Affinity Structure*/ +typedef struct acpi_srat_gen_init_struct { + u8 type; /* Type (5) */ + u8 length; /* Length in bytes (32) */ + u16 resv1; /* Reserved */ + u8 device_hdle_type; /* Device Handle Type */ + u32 proximity_domain; /* Proximity Domain */ + u32 device_hdle[4]; /* Device Handle of the Generic Initiator */ + u32 flags; /* */ + u32 resv2; +} __packed acpi_srat_gen_init_struct_t; + /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { acpi_header_t header; @@ -906,6 +949,10 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); +int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic); +int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu); +int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu); +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struct_t *gen, u8 node, u8 cpu); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index cb66c3b..08d3ef0 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -8,6 +8,7 @@ #include <imd.h> #include <lib.h> #include <stdlib.h> +#include <stdint.h>
/* The program loader passes on cbmem_top and the program entry point has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ @@ -15,17 +16,17 @@
static struct imd imd;
-void *cbmem_top(void) +uintptr_t cbmem_top(void) { if (ENV_ROMSTAGE) { static void *top; if (top) - return top; + return (uintptr_t)top; top = cbmem_top_chipset(); - return top; + return (uintptr_t) top; } if (ENV_POSTCAR || ENV_RAMSTAGE) - return (void *)_cbmem_top_ptr; + return (uintptr_t)_cbmem_top_ptr;
dead_code(); } diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index fee2a36..c748eb2 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -7,8 +7,9 @@ #include <cbmem.h> #include <ramdetect.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)(_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB)); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443..9a6ca59 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)(_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB)); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 2f8a4f8..86c265e 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -5,6 +5,7 @@ #include <arch/romstage.h> #include "memory.h" #include "fw_cfg.h" +#include <stdint.h>
#define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71 @@ -39,7 +40,7 @@ return tomk; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0;
@@ -47,7 +48,7 @@ if (!top) top = (uintptr_t)qemu_get_memory_size() * 1024;
- return (void *)top; + return (uintptr_t)top; }
/* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8..ecf29c1 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (uintptr_t)ptr; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1..9151912 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -9,8 +9,9 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t *cbmem_top_chipset(void) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -19,7 +20,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27;
- return (void *)tolm; + return (uintptr_t)tolm; }
void northbridge_write_smram(u8 smram); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 4fe3998..783f399 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -103,10 +103,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return (uintptr_t) top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb..bd79ab37 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <cbmem.h> #include "haswell.h" +#include <stdint.h>
static uintptr_t smm_region_start(void) { @@ -21,9 +22,9 @@ return tom & ~((1 << 20) - 1); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (uintptr_t)smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..2a83964 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -7,8 +7,9 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "i440bx.h" +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -48,7 +49,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return (uintptr_t)tom; }
void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 07aea98..9e7113b 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -58,10 +58,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return (uintptr_t) top_of_ram; }
/* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 406b9a9..191317f 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -10,6 +10,7 @@ #include <program_loading.h> #include <cpu/intel/smm_reloc.h> #include "ironlake.h" +#include <stdint.h>
static uintptr_t smm_region_start(void) { @@ -28,9 +29,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return (uintptr_t) smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 8da4ec9..ea562e2 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -10,6 +10,7 @@ #include <cpu/x86/smm.h> #include <program_loading.h> #include "sandybridge.h" +#include <stdint.h>
static uintptr_t smm_region_start(void) { @@ -17,9 +18,9 @@ return pci_read_config32(HOST_BRIDGE, TSEGMB); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (uintptr_t)smm_region_start(); }
static uintptr_t northbridge_get_tseg_base(void) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e..694bb9b 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -2,6 +2,7 @@
#define __SIMPLE_DEVICE__
+#include <stdint.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> @@ -113,10 +114,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9807905..5662241 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -14,6 +14,7 @@ #include <soc/northbridge.h> #include <soc/iomap.h> #include <amdblocks/acpimmio.h> +#include <stdint.h>
#if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 @@ -35,7 +36,7 @@ *size = BERT_REGION_MAX_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM);
@@ -43,7 +44,7 @@ return 0;
/* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return (uintptr_t)ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE - BERT_REGION_MAX_SIZE, 8*MiB); } diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16..5de9c79 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -4,9 +4,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return (uintptr_t)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..2e17ab8 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -5,6 +5,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <soc/iosf.h> +#include <stdint.h>
static uintptr_t smm_region_start(void) { @@ -16,9 +17,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return (uintptr_t) smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 6cfce43..5bc859b 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -3,6 +3,7 @@ #include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/iosf.h> +#include <stdint.h>
static size_t smm_region_size(void) { @@ -19,7 +20,7 @@ *size = smm_region_size(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +54,5 @@ */
smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return (uintptr_t)smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index bada5fd..77ff971 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -27,9 +27,9 @@ return tom; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return (uintptr_t) dpr_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e9..8fd7096 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -4,10 +4,11 @@ #include <commonlib/helpers.h> #include <symbols.h> #include <soc/emi.h> +#include <stdint.h>
#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return (uintptr_t )(MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS)); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f06..1236914 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <soc/display.h> #include <soc/sdram.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); -} + return (uintptr_t)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); +} \ No newline at end of file diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b2226..0f9cdce 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/addressmap.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr;
@@ -19,5 +20,5 @@ addr = end_mib << 20; }
- return (void *)addr; + return (uintptr_t)addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a..14189e7 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -2,6 +2,7 @@
#include <cbmem.h> #include <soc/soc_services.h> +#include <stdint.h>
static int cbmem_backing_store_ready;
@@ -10,7 +11,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -19,7 +20,7 @@ * for loading ipq blobs before DRAM is initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return (uintptr_t)NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf8..c3b0fa8 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -2,6 +2,7 @@
#include <cbmem.h> #include <soc/soc_services.h> +#include <stdint.h>
static int cbmem_backing_store_ready;
@@ -10,7 +11,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -20,7 +21,7 @@ * initialized). */ if (cbmem_backing_store_ready == 0) - return NULL; + return (uintptr_t)NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b..08b18eb 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return (uintptr_t)((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37..d25433e 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)((uintptr_t)4 * GiB); } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 4b9eb37..d25433e 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)((uintptr_t)4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114..7e52e48 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -5,9 +5,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) + uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - MAX_DRAM_ADDRESS); + return (uintptr_t)(MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + MAX_DRAM_ADDRESS)); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80..ec4f973 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/cpu.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)((get_fb_base_kb() * KiB)); } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80..ec4f973 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/cpu.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)((get_fb_base_kb() * KiB)); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af04130..7e98fcd 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -5,9 +5,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, - FU540_MAXDRAM); + return (uintptr_t)(MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + FU540_MAXDRAM)); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443..9a6ca59 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)(_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB)); }