[coreboot-gerrit] Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI

[Jenny Tc (Code Review)]

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29775

Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
......................................................................

SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI

With Lazy SCI mask, EC and OS can take over iniitializing the SCI
events done by B2_SMI interrupt.

Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5
Signed-off-by: Jenny TC 
---
M src/ec/google/chromeec/smihandler.c
M src/soc/intel/common/Kconfig
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29775/1

diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c
index cab7192..d608db5 100644
--- a/src/ec/google/chromeec/smihandler.c
+++ b/src/ec/google/chromeec/smihandler.c
@@ -99,6 +99,7 @@
    google_chromeec_get_device_current_events();
 }

+#if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI)
 void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask)
 {
    switch (apmc) {
@@ -114,3 +115,6 @@
    	break;
    }
 }
+#else
+void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask) { }
+#endif
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 27d3f59..9097195 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -65,6 +65,10 @@
    bool
    default n

+config SOC_INTEL_BYPASS_PORT_B2_SMI
+        bool
+	default n
+
 config TPM_TIS_ACPI_INTERRUPT
    int
    help