[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: add empty ramstage FCH support

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50094 )

Change subject: soc/amd/cezanne: add empty ramstage FCH support
......................................................................

soc/amd/cezanne: add empty ramstage FCH support

Signed-off-by: Felix Held 
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/chip.c
A src/soc/amd/cezanne/fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
4 files changed, 21 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50094/1

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index bcf1d72..9422a4d 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -25,6 +25,7 @@
 romstage-y	+= uart.c

ramstage-y	+= chip.c
+ramstage-y	+= fch.c
 ramstage-y      += fsp_params.c
 ramstage-y	+= gpio.c
 ramstage-y      += reset.c
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 70df778..fd93089 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -2,6 +2,7 @@

#include <device/device.h>
 #include <fsp/api.h>
+#include <soc/southbridge.h>
 #include <types.h>
 #include "chip.h"

@@ -12,10 +13,13 @@
 static void soc_init(void *chip_info)
 {
    fsp_silicon_init(false); /* no S3 support yet */
+
+	fch_init(chip_info);
 }

static void soc_final(void *chip_info)
 {
+	fch_final(chip_info);
 }

struct chip_operations soc_amd_cezanne_ops = {
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
new file mode 100644
index 0000000..f853ece
--- /dev/null
+++ b/src/soc/amd/cezanne/fch.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/southbridge.h>
+
+void fch_init(void *chip_info)
+{
+}
+
+void fch_final(void *chip_info)
+{
+}
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 2a294e9..6949fa5 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -30,9 +30,12 @@
 /* IO 0xf0 NCP Error */
 #define   NCP_WARM_BOOT			(1 << 7) /* Write-once */

-void enable_aoac_devices(void);
-void wait_for_aoac_enabled(unsigned int dev);
 void fch_pre_init(void);
 void fch_early_init(void);
+void fch_init(void *chip_info);
+void fch_final(void *chip_info);
+
+void enable_aoac_devices(void);
+void wait_for_aoac_enabled(unsigned int dev);

#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */