[coreboot-gerrit] Change in coreboot[master]: nb/amd/pi/00730F01: enable ACS and AER for PCIe ports

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35313 )

Change subject: nb/amd/pi/00730F01: enable ACS and AER for PCIe ports
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Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... 
File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... 
PS7, Line 794: 	value |= (BIT(5) | BIT(6));
> But you write `AER (bit 5)` explicitly. […]

I missed the comment... Looked at BKDG that had these bits undocumented and prematurely answered without noticing my comment... Some of BKDgs have at least AER documented.