Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3842
-gerrit
commit d71234fcb2d422e72b5a5daa61d3e7b65d6de3a4 Author: Bruce Griffith bruce.griffith@se-eng.com Date: Mon Jul 29 20:59:06 2013 -0600
AMD Hudson: Add wrapper functions to enable LPC Super I/O ports
The current method for AMD platforms is to add 0xCD6/0xCD7 I/O writes into the mainboard code. Wrapper code was added at some point to enable Port 80s using a function. This change does the same, providing a call to enable the Super I/O ports with a similar function [hudson_lpc_superio()].
Change-Id: I796c0b2321af07da1b15645ba6d541fea614112f Signed-off-by: Bruce Griffith bruce.griffith@se-eng.com Reviewed-by: Dave Frodin dave.frodin@se-eng.com --- src/southbridge/amd/agesa/hudson/early_setup.c | 33 ++++++++++++++++++++------ src/southbridge/amd/agesa/hudson/hudson.h | 1 + 2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..df5835c 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -29,17 +29,36 @@ #include <cbmem.h> #include "hudson.h"
-void hudson_lpc_port80(void) +static device_t hudson_lpc_enable(void) { - u8 byte; device_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + outb(0xEC, PM_INDEX); + outb(inb(PM_DATA) | 1, PM_DATA); + + /* Locate the LPC controller (0x1002, 0x439D) */ + dev = PCI_DEV(0, 0x14, 3); + + return dev; +} + + +void hudson_lpc_superio(void) +{ + device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable Super I/O configuration in pci function 3 configuration space. */ + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); +} + +void hudson_lpc_port80(void) +{ + device_t dev = hudson_lpc_enable(); + u8 byte;
/* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 686dbb5..7a6ed57 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -57,6 +57,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#ifdef __PRE_RAM__ +void hudson_lpc_superio(void); void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);