Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Pratikkumar Prajapati, Subrata Banik, Tarun Tuli.
Hello Pratikkumar Prajapati,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/77239?usp=email
to review the following change.
Change subject: soc/intel/meteorlake: Implement cleanup and rearm functions ......................................................................
soc/intel/meteorlake: Implement cleanup and rearm functions
cpu_cl_cleanup() function checks if the SOC supports storage-off feature. This feature allows to turn off PUNIT SSRAM to save power. Enable the storage-off if it's supported. Enabling it also clears the crashlog records from PUNIT SSRAM.
cpu_cl_rearm() function rearms the CPU crashlog.
BUG=b:262501347 TEST=Able to build REX. Verified both features get asserted.
Change-Id: Id9ba0f5db0b5d2bd57a7a21f178ef1e86ca63fae Signed-off-by: Pratikkumar Prajapati pratikkumar.v.prajapati@intel.corp-partner.google.com --- M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/meteorlake/include/soc/crashlog.h 2 files changed, 104 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/77239/1
diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index ce8ad54..657cd7d 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> +#include <delay.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -27,10 +28,13 @@ static pmc_crashlog_desc_table_t descriptor_table; static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; +static u32 disc_tab_addr;
-u32 __weak cl_get_cpu_mb_int_addr(void) + +static u64 get_disc_tab_header(u32 addr) { - return CRASHLOG_MAILBOX_INTF_ADDRESS; + return ((u64)read32((u32 *) addr) + + ((u64)read32((u32 *)(addr + 4)) << 32)); }
/* Get the SRAM BAR. */ @@ -371,7 +375,7 @@
static bool cpu_cl_gen_discovery_table(void) { - u32 bar_addr = 0, disc_tab_addr = 0, disc_tab_offset = 0; + u32 bar_addr = 0, disc_tab_offset = 0; bar_addr = cl_get_cpu_bar_addr();
if (!bar_addr) @@ -468,6 +472,89 @@ return m_pmc_crashLog_size + m_cpu_crashLog_size + m_ioe_crashLog_size; }
+static u32 get_control_status_interface(void) +{ + if (disc_tab_addr) + return (disc_tab_addr + 5 * sizeof(u32)); + return 0; +} + +int cpu_cl_clear_data(void) +{ + return 0; +} + +static bool wait_and_check(u32 bit_mask) +{ + u32 stall_cnt = 0; + + do { + cpu_cl_disc_tab.header.data = get_disc_tab_header(disc_tab_addr); + udelay(CPU_CRASHLOG_WAIT_STALL); + stall_cnt ++; + } while (cpu_cl_disc_tab.header.data && bit_mask == 0 && + stall_cnt < CPU_CRASHLOG_WAIT_TIMEOUT); + + return (cpu_cl_disc_tab.header.data && bit_mask); +} + +void cpu_cl_rearm(void) +{ + u32 ctrl_sts_intfc_addr = get_control_status_interface(); + + if (!ctrl_sts_intfc_addr) { + printk(BIOS_ERR,"CPU crashlog control and status interface address not valid\n"); + return; + } + + cl_punit_control_interface_t punit_ctrl_intfc; + memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t)); + punit_ctrl_intfc.fields.set_re_arm = 1; + + write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); + + if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK)) { + printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n"); + } else { + printk(BIOS_DEBUG, "CPU crashlog re_arm asserted\n"); + } + + return; +} + +void cpu_cl_cleanup(void) +{ + u32 ctrl_sts_intfc_addr = get_control_status_interface(); + + if (!ctrl_sts_intfc_addr) { + printk(BIOS_ERR,"CPU crashlog control and status interface address not valid\n"); + return; + } + + /* if storage-off is supported, turn off the PUNIT SRAM + * stroage to save power. This clears crashlog records also. + */ + + if (!cpu_cl_disc_tab.header.fields.storage_off_support) { + printk(BIOS_INFO,"CPU crashlog storage_off_supported\n"); + return; + } + + cl_punit_control_interface_t punit_ctrl_intfc; + memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t)); + punit_ctrl_intfc.fields.set_storage_off = 1; + write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); + + + if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK)) { + printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n"); + } else { + printk(BIOS_DEBUG, "CPU crashlog storage_off asserted\n"); + } + + return; +} + pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void) { return discovery_buf; diff --git a/src/soc/intel/meteorlake/include/soc/crashlog.h b/src/soc/intel/meteorlake/include/soc/crashlog.h index 93b2af9..bc593c66 100644 --- a/src/soc/intel/meteorlake/include/soc/crashlog.h +++ b/src/soc/intel/meteorlake/include/soc/crashlog.h @@ -18,6 +18,20 @@ /* CPU CrashLog MMIO Registers */ #define CRASHLOG_MAILBOX_INTF_ADDRESS 0x6038
+#define CRASHLOG_PUNIT_STORAGE_OFF_MASK BIT(24) +#define CRASHLOG_RE_ARM_STATUS_MASK BIT(25) #define CRASHLOG_CONSUMED_MASK BIT(31)
+typedef union { + struct { + u32 reserved1 :27; + u32 set_storage_off :1; + u32 set_re_arm :1; + u32 reserved2 :1; + u32 set_clr :1; + u32 reserved3 :1; + } fields; + u32 data; +} __packed cl_punit_control_interface_t; + #endif /* _SOC_METEORLAKE_CRASHLOG_H_ */