Attention is currently required from: Marx Wang, Gaggery Tsai, Nico Huber, Angel Pons, Kane Chen. Hello Gaggery Tsai, build bot (Jenkins), Paul Menzel, Angel Pons, Kane Chen, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48510
to look at the new patch set (#19).
Change subject: soc/intel/apollolake: Provide the option to mitigate Row Hammer vulnerability ......................................................................
soc/intel/apollolake: Provide the option to mitigate Row Hammer vulnerability
We can enable 2x refresh rate and low watermark in order to mitigate Row Hammer vulnerability for the boards with specific DRAMs. To enable it, we can add "enable_row_hammer_mitigation" attribute in board's lpddr4 memory config. for example:
static const struct lpddr4_sku cbi_skus[] = { /* Dual Channel Config 4GiB System Capacity */ ............. ................................ /* Dual Channel Config 8GiB System Capacity */ [1] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_16Gb_DENSITY, .ch1_rank_density = LP4_16Gb_DENSITY, .enable_row_hammer_mitigation = 1, },
CQ-DEPEND=chrome-internal:3456385 BUG=b:152151369 TEST=add "enable_row_hammer_mitigation=1" attribute for specific DRAMs, build the image and run "suspend_stress_test" with memory check for 2500 cycles.
Signed-off-by: Marx Wang marx.wang@intel.com Change-Id: I0235fc7906626f28f14367c283433e5b066cc89a --- M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/meminit.c M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h 3 files changed, 34 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48510/19