Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48080 )
Change subject: mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG@12 PS4, Line 12: Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low Why are these being driven low? Are these the CLK pins?
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 54: free running CLK Just for my education: What is a free running CLK?
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/gpio.c:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 76: PAD_CFG_GPO Shouldn't this be NF?
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 78: PAD_CFG_GPO Same here.