Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34988 )
Change subject: mediatek/mt8183: Implement the dramc init setting ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... PS9, Line 679: u8 MR01Value[FSP_MAX] = {0x26, 0x56}; : u8 MR13Value = (1 << 4) | (1 << 3);
Is this defined outside a function for a particular reason?
dramc_pi_calibration_api.c will have to use it in the next CL. See https://review.coreboot.org/c/coreboot/+/34332/30/src/soc/mediatek/mt8183/dr....
https://review.coreboot.org/c/coreboot/+/34988/9/src/soc/mediatek/mt8183/dra... PS9, Line 1343: : if (freq_group == LP4X_DDR1600) : dramc_setting_DDR1600(); : else if (freq_group == LP4X_DDR2400) : dramc_setting_DDR2400(); : else if (freq_group == LP4X_DDR3600) : dramc_setting_DDR3600();
This can also be a 'switch' statement. […]
Ping @huayang