[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update PCH and CPU PCIe RP table

[Furquan Shaikh (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )

Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table
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Patch Set 4:

(1 comment)

File src/soc/intel/alderlake/pcie_rp.c:

https://review.coreboot.org/c/coreboot/+/49021/comment/d5d3138e_ea1c5d89 
PS2, Line 18: /* TODO check how to determine CPU PCIE port */
> If the indexes match the port numbers in the link capabilities

(they do on the PCH, off-by-one), we could read them from the
config space.

It is not clear from the documentation how the ports are numbered in the link capabilities. Probably someone with access to the hardware can play with this to get a better understanding. EDS says 01h for both 0/1/0 as well as 0/6/*.