[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/cannonlake: Add missing USB port aliases

[Maxim (Code Review)]

Attention is currently required from: Mario Scheithauer, Maxim, Paul Menzel, Sean Rhodes, Tim Crawford.

Hello Mario Scheithauer, Paul Menzel, Sean Rhodes, Tim Crawford, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84442?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/cannonlake: Add missing USB port aliases
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soc/intel/cannonlake: Add missing USB port aliases

FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable
array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2].

[1] src/soc/intel/cannonlake/chip.h
[2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h

Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/cannonlake/chipset_pch_h.cb
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84442/5