Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41604 )
Change subject: mb/ocp/tiogapass: Implement set POST start/end command ......................................................................
mb/ocp/tiogapass: Implement set POST start/end command
Implemented sending POST start and POST end command to BMC in ramstage.
Tested=Read POST command in OpenBMC, if success message may show as below,
root@bmc:~# cat /var/log/messages |grep -i "POST" Aug 10 00:11:24 bmc user.info ipmid: POST Start Event for Payload#1 Aug 10 00:11:28 bmc user.info ipmid: POST End Event for Payload#1 root@bmc:~#
Signed-off-by: TimChu Tim.Chu@quantatw.com Change-Id: Ia283c5e8d539bfeb47a73d32d8bfb5e666f27170 --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41604/1
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 5cb2421..2ec47ed 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -9,6 +9,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_OCP select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 19dba55..35e74b0 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -77,6 +77,9 @@ register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end + chip drivers/ocp/ipmi # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus