Marius Genheimer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32712
Change subject: mb/gigabyte/GA-SBCAP3450: add mainboard ......................................................................
mb/gigabyte/GA-SBCAP3450: add mainboard
Change-Id: I04fe3a9849b99225b78c38d46434e7b2e629c582 Signed-off-by: Marius Genheimer mail@f0wl.cc --- A src/mainboard/gigabyte/ga-sbcap3450/Kconfig A src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name A src/mainboard/gigabyte/ga-sbcap3450/board_info.txt 3 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32712/1
diff --git a/src/mainboard/gigabyte/ga-sbcap3450/Kconfig b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig new file mode 100644 index 0000000..7ea0547 --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig @@ -0,0 +1,68 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Intel Corporation +## Copyright (C) 2015 Google Inc. +## Copyright (C) 2019 Marius Genheimer mail@f0wl.cc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_GIGABYTE_SBCAP3450 + +config BOARD_SPECIFIC_OPTIONS + + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_8192 + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE + select USE_BLOBS + +config MAINBOARD_DIR + string + default "gigabyte/ga-sbcap3450" + +config MAINBOARD_PART_NUMBER + string + default "SBCAP3450" + +config MAINBOARD_FAMILY + string + default "Gigabyte_SBC" + +config SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config SUBSYSTEM_DEVICE_ID + hex + default 0xb005 + +config MAX_CPUS + int + default 4 + +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 256 #DDR3 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +endif diff --git a/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name new file mode 100644 index 0000000..16f0432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_SBCAP3450 + bool "GA-SBCAP3450" diff --git a/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt b/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt new file mode 100644 index 0000000..762164c --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Gigabyte +Board name: GA-SBCAP3450 +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +ROM package: SOIC-8 +Release year: 2018