Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... PS9, Line 167: /* Cache the ROM as WP just below 4GiB. */
Yes. And cbmem -t with POSTCAR_STAGE=y for comparison.
localhost ~ # cbmem -t 58 entries total:
0:1st timestamp 12,239 100:start of postcar 307,098 (890) 101:end of postcar 307,099 (0) 99:selfboot jump 647,489 (465)
I am pretty sure this was not with POSTCAR_STAGE=y. Nevertheless, it's now 635ms to enter payload, while it was 650ms before. So I assume this was POSTCAR_STAGE=n with TSEG marked WB cacheable?
if you have trust issue, then i would recommend you to find your HW and identify the data.
Nah.. I just got confused because there were no "starting to load postcar" or "finished loading postcar" timestamps.
I am still waiting for cbmem -t from POSTCAR_STAGE=y and TSEG marked WB cacheable. That should be your reference point for the commit message.
As i have told, my last shared data was with POSTCAR_STAGE=y and https://review.coreboot.org/c/coreboot/+/34995 CL.
OK, good. It was CB:34995 + CB:34791 and I got confused about the entries.
For comparison, I would want to see cbmem -t posted in CB:34995 and CB:34752 comments as well, so we get the correct numbers presented in the commit messages.
Those would be just TSEG marked WB (CB:34995) and the POSTCAR_STAGE=n case (CB:34995 + CB:34791 + CB:34752).