Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )
Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/7ce0ba4a_a57a3a5e PS1, Line 54: HIGH
They get toggled by the FSP. […]
But why? In my opinion that is not the right direction to take. All the GPIOs must be configured correctly by coreboot before handing over to FSP/AGESA to initialize root ports. There are requirements w.r.t. timings which are best handled by coreboot rather than spreading the configuration across coreboot and FSP/AGESA.
https://review.coreboot.org/c/coreboot/+/52115/comment/eb81ba8d_81d4d31c PS1, Line 169: /* EN_PP3300_WLAN */
I'm sure there are, but we haven't looked at that yet. […]
Why is this dependent on PSP verstage?