Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45045 )
Change subject: soc/amd/picasso: Move DRAM end to after transfer buffer ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45045/1//COMMIT_MSG@11 PS1, Line 11: transferred Could you please provide symbol addresses for before and after? nm on the resulting elfs from the build will provide you that. Grep for _epsp_sharedmem_dram:
$ nm coreboot-builds/GOOGLE_TREMBYLE/cbfs/fallback/bootblock.debug | grep _epsp_sharedmem_dram 02019000 T _epsp_sharedmem_dram
I see the following w/o your change in bootblock: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram
all x86 stages have the same addreses. However, are these addresses being relocated when being added to cbfs?