Hello Marshall Dawson,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40298
to review the following change.
Change subject: soc/amd/picasso: Notify PSP system is going to sleep state ......................................................................
soc/amd/picasso: Notify PSP system is going to sleep state
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a --- M src/soc/amd/picasso/smihandler.c 1 file changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/40298/1
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index e4d1c86..f29fffb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -145,6 +145,30 @@ smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); }
+static void send_sx_info(uint8_t slptyp) +{ + uint8_t sx; + + switch (slptyp) { + case ACPI_S0: + sx = 0; + break; + case ACPI_S3: + sx = 3; + break; + case ACPI_S4: + sx = 4; + break; + case ACPI_S5: + sx = 5; + break; + default: + return; + } + + psp_notify_sx_info(sx); +} + static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; @@ -220,12 +244,16 @@ reg32); } /* if (CONFIG(ELOG_GSMI)) */
+ send_sx_info(slp_typ); + /* * An IO cycle is required to trigger the STPCLK/STPGNT * handshake when the Pm1 write is reissued. */ outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK)); hlt(); + } else { + send_sx_info(slp_typ); } }