[coreboot-gerrit] Change in ...coreboot[master]: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33549

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
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[RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

Most mainboards do nothing but setting up a similar decode range so
move it to a common place. All IO ports below 0x1000 are allocated to
the LPC device by default so this should not be an issue.

Lynxpoint does this too.

TODO remove most mainboard specific setups.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/bd82x6x/early_pch.c
1 file changed, 12 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/1

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 0082c91..ef3ee77 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -258,8 +258,16 @@
    write_pmbase16(TCO1_CNT, 1 << 11);	/* halt timer */
 }

-static void pch_enable_lpc_gen_decode(void)
+static void pch_enable_lpc_decode(void)
 {
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+	/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN
+		| KBC_LPC_EN | MC_LPC_EN;
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
+
    const struct device *dev = pcidev_on_root(0x1f, 0);
    const struct southbridge_intel_bd82x6x_config *config = NULL;

@@ -279,9 +287,10 @@

void early_pch_init(void)
 {
-	pch_enable_lpc();

-	pch_enable_lpc_gen_decode();
+	pch_enable_lpc_decode();
+
+	pch_enable_lpc();

pch_enable_bars();