Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )
Change subject: soc/intel/cannonlake: Pass more SPI options to FSP. ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h@41 PS2, Line 41: #define SOC_INTEL_CML_SPI_DEV_MAX 3 What does this represent? Generic SPI devices? PchSerialIoSpiMAX == 2 but this macro is 3. Why is there a difference? Such discrepancies should be commented accordingly here. There seems to be an issue in the upd settings. Has intel provide an explanation for 3 vs 2 array sizes?
https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/fsp_params.... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/fsp_params.... PS2, Line 96: config->SerialIoSpi2CsPolarity[i]; What is utilizing the SerialIoSpiXCsEnable fields?