yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34515 )
Change subject: mediatek/mt8183: common display driver code ......................................................................
mediatek/mt8183: common display driver code
BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: Ie5709ab6e263caa21fdf7e799dc2ee884ffaf800 Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com --- M src/mainboard/google/kukui/mainboard.c A src/soc/mediatek/common/ddp.c A src/soc/mediatek/common/include/soc/ddp.h M src/soc/mediatek/mt8173/Makefile.inc R src/soc/mediatek/mt8173/include/soc/mt8173_ddp.h R src/soc/mediatek/mt8173/mt8173_ddp.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h R src/soc/mediatek/mt8183/include/soc/mt8183_ddp.h R src/soc/mediatek/mt8183/mt8183_ddp.c 10 files changed, 285 insertions(+), 384 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/34515/1
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 8a8cdce..3dcdb16 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <edid.h> #include <gpio.h> -#include <soc/ddp.h> +#include <soc/mt8183_ddp.h> #include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c new file mode 100644 index 0000000..ab17594 --- /dev/null +++ b/src/soc/mediatek/common/ddp.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <edid.h> +#include <stdlib.h> +#include <stddef.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +void ovl_layer_enable(u32 idx) +{ + write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); +} + +void rdma_start(u32 idx) +{ + setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); +} + +void rdma_config(u32 idx, u32 width, u32 height, u32 pixel_clk) +{ + u32 threshold; + u32 reg; + u32 fifo_size; + + /* Config width */ + clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); + + /* Config height */ + clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + fifo_size = RDMA_FIFO_SIZE_0 * KiB; + + threshold = pixel_clk * 4 * 7 / 1000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[idx]->fifo_con, reg); +} + +void color_start(u32 width, u32 height) +{ + write32(&disp_color[0]->width, width); + write32(&disp_color[0]->height, height); + write32(&disp_color[0]->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color[0]->start, BIT(0)); +} + +void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[idx]->layer[0].con, fmt << 12); + write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(idx); +} diff --git a/src/soc/mediatek/common/include/soc/ddp.h b/src/soc/mediatek/common/include/soc/ddp.h new file mode 100644 index 0000000..846cdeb --- /dev/null +++ b/src/soc/mediatek/common/include/soc/ddp.h @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include <soc/addressmap.h> +#include <types.h> + +#if CONFIG_SOC_MEDIATEK_MT8183 +#define RDMA_FIFO_SIZE_0 5 +#else +#define RDMA_FIFO_SIZE_0 8 +#endif + + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u8 reserved0[8]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u8 reserved8[16]; + struct { + u32 ctrl; + u32 mem_start_trig; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u8 reserved[12]; + } rdma[4]; + u8 reserved12[148]; + u32 debug_mon_sel; + u8 reserved13[8]; + u32 rdma_mem_gmc_setting2[4]; + u8 reserved14[16]; + u32 dummy; + u8 reserved15[60]; + u32 flow_ctrl_dbg; + u32 addcon_dbg; + u32 outmux_dbg; + u32 rdma_dbg[4]; + u8 reserved16[3300]; + u32 l0_addr; + u8 reserved17[28]; + u32 l1_addr; + u8 reserved18[28]; + u32 l2_addr; + u8 reserved19[28]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL1_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u8 reserved0[8]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u8 reserved1[4]; + u32 mem_con; + u32 mem_start_addr; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_slow_con; + u32 mem_gmc_setting_1; + u8 reserved2[4]; + u32 fifo_con; + u8 reserved3[16]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma[2] = { + (void *)DISP_RDMA0_BASE, + (void *)DISP_RDMA1_BASE, +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color[2] = { + (void *)DISP_COLOR0_BASE, +}; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color); +void ovl_layer_enable(u32 idx); +void rdma_start(u32 idx); +void rdma_config(u32 idx, u32 width, u32 height, u32 pixel_clk); +void color_start(u32 width, u32 height); +void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height); + +#endif diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0ffa196..1342ef8 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -81,7 +81,8 @@
ramstage-y += ../common/usb.c usb.c
-ramstage-y += ddp.c +ramstage-y += ../common/ddp.c +ramstage-y += mt8173_ddp.c ramstage-y += dsi.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/mt8173_ddp.h similarity index 78% rename from src/soc/mediatek/mt8173/include/soc/ddp.h rename to src/soc/mediatek/mt8173/include/soc/mt8173_ddp.h index 0bd832e..fb032a1 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/mt8173_ddp.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */
-#ifndef _DDP_REG_H_ -#define _DDP_REG_H_ +#ifndef _MT8173_DDP_REG_H_ +#define _MT8173_DDP_REG_H_
#include <soc/addressmap.h> #include <types.h> @@ -254,100 +254,6 @@ MUTEX_MOD_DISP_UFOE | MUTEX_MOD_DISP_OD, };
-struct disp_ovl_regs { - u32 sta; - u32 inten; - u32 intsta; - u32 en; - u32 trig; - u32 rst; - u8 reserved0[8]; - u32 roi_size; - u32 datapath_con; - u32 roi_bgclr; - u32 src_con; - struct { - u32 con; - u32 srckey; - u32 src_size; - u32 offset; - u32 reserved0; - u32 pitch; - u32 reserved1[2]; - } layer[4]; - u8 reserved8[16]; - struct { - u32 ctrl; - u32 mem_start_trig; - u32 mem_gmc_setting; - u32 mem_slow_con; - u32 fifo_ctrl; - u8 reserved[12]; - } rdma[4]; - u8 reserved12[148]; - u32 debug_mon_sel; - u8 reserved13[8]; - u32 rdma_mem_gmc_setting2[4]; - u8 reserved14[16]; - u32 dummy; - u8 reserved15[60]; - u32 flow_ctrl_dbg; - u32 addcon_dbg; - u32 outmux_dbg; - u32 rdma_dbg[4]; - u8 reserved16[3300]; - u32 l0_addr; - u8 reserved17[28]; - u32 l1_addr; - u8 reserved18[28]; - u32 l2_addr; - u8 reserved19[28]; - u32 l3_addr; -}; - -check_member(disp_ovl_regs, l3_addr, 0xFA0); -static struct disp_ovl_regs *const disp_ovl[2] = { - (void *)DIS_OVL0_BASE, (void *)DIS_OVL1_BASE -}; - -struct disp_rdma_regs { - u32 int_enable; - u32 int_status; - u8 reserved0[8]; - u32 global_con; - u32 size_con_0; - u32 size_con_1; - u32 target_line; - u8 reserved1[4]; - u32 mem_con; - u32 mem_start_addr; - u32 mem_src_pitch; - u32 mem_gmc_setting_0; - u32 mem_slow_con; - u32 mem_gmc_setting_1; - u8 reserved2[4]; - u32 fifo_con; - u8 reserved3[16]; - u32 cf[3][3]; - u32 cf_pre_add[3]; - u32 cf_post_add[3]; - u32 dummy; - u32 debug_out_sel; -}; - -enum { - RDMA_ENGINE_EN = BIT(0), - RDMA_FIFO_UNDERFLOW_EN = BIT(31), - RDMA_MEM_GMC = 0x40402020, -}; - -check_member(disp_rdma_regs, debug_out_sel, 0x94); -static struct disp_rdma_regs *const disp_rdma[3] = { - (void *)DISP_RDMA0_BASE, - (void *)DISP_RDMA1_BASE, - (void *)DISP_RDMA2_BASE -}; - struct disp_od_regs { u32 en; u32 reset; @@ -436,22 +342,6 @@ COLOR_SEQ_SEL = BIT(13), };
-enum OVL_INPUT_FORMAT { - OVL_INFMT_RGB565 = 0, - OVL_INFMT_RGB888 = 1, - OVL_INFMT_RGBA8888 = 2, - OVL_INFMT_ARGB8888 = 3, - OVL_INFMT_UYVY = 4, - OVL_INFMT_YUYV = 5, - OVL_INFMT_UNKNOWN = 16, - - OVL_COLOR_BASE = 30, - OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, - OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, - OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, - OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, -}; - void mtk_ddp_init(bool dual_dsi_mode); void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode);
diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/mt8173_ddp.c similarity index 66% rename from src/soc/mediatek/mt8173/ddp.c rename to src/soc/mediatek/mt8173/mt8173_ddp.c index 0b78c3e..6acdb3b 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/mt8173_ddp.c @@ -20,9 +20,6 @@ #include <soc/addressmap.h> #include <soc/ddp.h>
-#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) -#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) - static void disp_config_main_path_connection(bool dual_dsi_mode) { write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0); @@ -50,52 +47,6 @@ write32(&disp_mutex->mutex[0].en, BIT(0)); }
-static void ovl_set_roi(u32 width, u32 height, u32 color) -{ - write32(&disp_ovl[0]->roi_size, height << 16 | width); - write32(&disp_ovl[0]->roi_bgclr, color); -} - -static void ovl_layer_enable(void) -{ - write32(&disp_ovl[0]->rdma[0].ctrl, BIT(0)); - write32(&disp_ovl[0]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); - - setbits_le32(&disp_ovl[0]->src_con, BIT(0)); -} - -static void rdma_start(void) -{ - setbits_le32(&disp_rdma[0]->global_con, RDMA_ENGINE_EN); -} - -static void rdma_config(u32 width, u32 height, u32 pixel_clk) -{ - u32 threshold; - u32 reg; - - /* Config width */ - clrsetbits_le32(&disp_rdma[0]->size_con_0, 0x1FFF, width); - - /* Config height */ - clrsetbits_le32(&disp_rdma[0]->size_con_1, 0xFFFFF, height); - - /* - * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the - * FIFO pseudo size reset default of 8 KiB. Set the output threshold to - * 6 microseconds with 7/6 overhead to account for blanking, and with a - * pixel depth of 4 bytes: - */ - - threshold = pixel_clk * 4 * 7 / 1000; - - reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(8 * KiB) | - RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - - write32(&disp_rdma[0]->fifo_con, reg); -} - static void od_start(u32 width, u32 height) { write32(&disp_od->size, width << 16 | height); @@ -115,28 +66,11 @@ } }
-static void color_start(u32 width, u32 height) -{ - write32(&disp_color[0]->width, width); - write32(&disp_color[0]->height, height); - write32(&disp_color[0]->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); - write32(&disp_color[0]->start, BIT(0)); -} - static void split_start(void) { write32(&disp_split->start, 1); }
-static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) -{ - write32(&disp_ovl[0]->layer[0].con, fmt << 12); - write32(&disp_ovl[0]->layer[0].src_size, height << 16 | width); - write32(&disp_ovl[0]->layer[0].pitch, (width * bpp) & 0xFFFF); - - ovl_layer_enable(); -} - static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk, bool dual_dsi_mode) { diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 15ad154..63f8b6b 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -42,7 +42,8 @@
ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c -ramstage-y += ddp.c +ramstage-y += ../common/ddp.c +ramstage-y += mt8183_ddp.c ramstage-y += dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 75202dd..708a2a6 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -54,20 +54,20 @@ IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, - MMSYS_BASE = IO_PHYS + 0x04000000, - DISP_OVL0_BASE = IO_PHYS + 0x04008000, - DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000, - DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, - DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, - DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, - DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, - DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, - DISP_AAL0_BASE = IO_PHYS + 0x04010000, - DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, - DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL1_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, DSI_BASE = IO_PHYS + 0x04014000, - DISP_MUTEX_BASE = IO_PHYS + 0x04016000, - SMI_LARB0 = IO_PHYS + 0x04017000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, };
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/mt8183_ddp.h similarity index 67% rename from src/soc/mediatek/mt8183/include/soc/ddp.h rename to src/soc/mediatek/mt8183/include/soc/mt8183_ddp.h index 501efa2..bbbabd7 100644 --- a/src/soc/mediatek/mt8183/include/soc/ddp.h +++ b/src/soc/mediatek/mt8183/include/soc/mt8183_ddp.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */
-#ifndef _DDP_REG_H_ -#define _DDP_REG_H_ +#ifndef _MT8183_DDP_REG_H_ +#define _MT8183_DDP_REG_H_
#include <soc/addressmap.h> #include <types.h> @@ -161,109 +161,6 @@ MUTEX_SOF_DPI0 = 2, };
-struct disp_ovl_regs { - u32 sta; - u32 inten; - u32 intsta; - u32 en; - u32 trig; - u32 rst; - u32 reserved_0x018[2]; - u32 roi_size; - u32 datapath_con; - u32 roi_bgclr; - u32 src_con; - struct { - u32 con; - u32 srckey; - u32 src_size; - u32 offset; - u32 reserved0; - u32 pitch; - u32 reserved1[2]; - } layer[4]; - u32 reserved_0x0B0[4]; - struct { - u32 ctrl; - u32 reserved0; - u32 mem_gmc_setting; - u32 mem_slow_con; - u32 fifo_ctrl; - u32 reserved1[3]; - } rdma[4]; - u32 reserved_0x140[880]; - u32 reserved_0xF00[16]; - u32 l0_addr; - u32 reserved_0xF44[7]; - u32 l1_addr; - u32 reserved_0xF64[7]; - u32 l2_addr; - u32 reserved_0xF84[7]; - u32 l3_addr; -}; - -check_member(disp_ovl_regs, l3_addr, 0xFA0); -static struct disp_ovl_regs *const disp_ovl[2] = { - (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE -}; - -struct disp_rdma_regs { - u32 int_enable; - u32 int_status; - u32 reserved0[2]; - u32 global_con; - u32 size_con_0; - u32 size_con_1; - u32 target_line; - u32 reserved1; - u32 mem_con; - u32 reserved2; - u32 mem_src_pitch; - u32 mem_gmc_setting_0; - u32 mem_gmc_setting_1; - u32 mem_slow_con; - u32 mem_gmc_setting_2; - u32 fifo_con; - u32 reserved3[4]; - u32 cf[3][3]; - u32 cf_pre_add[3]; - u32 cf_post_add[3]; - u32 dummy; - u32 debug_out_sel; -}; - -enum { - RDMA_ENGINE_EN = BIT(0), - RDMA_FIFO_UNDERFLOW_EN = BIT(31), - RDMA_FIFO_SIZE_0 = 5, /* 5K */ - RDMA_VREFRESH = 60, /* vrefresh 60HZ */ - RDMA_MEM_GMC = 0x40402020, -}; - -check_member(disp_rdma_regs, debug_out_sel, 0x94); -static struct disp_rdma_regs *const disp_rdma[2] = { - (void *)DISP_RDMA0_BASE, - (void *)DISP_RDMA1_BASE, -}; - -struct disp_color_regs { - u8 reserved0[1024]; - u32 cfg_main; - u8 reserved1[2044]; - u32 start; - u8 reserved2[76]; - u32 width; - u32 height; -}; - -check_member(disp_color_regs, height, 0xC54); -static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE; - -enum { - COLOR_BYPASS_ALL = BIT(7), - COLOR_SEQ_SEL = BIT(13), -}; - struct disp_pq_regs { u32 en; u32 reset; @@ -293,22 +190,6 @@ SMI_LARB_NON_SEC_CON = 0x380, };
-enum OVL_INPUT_FORMAT { - OVL_INFMT_RGB565 = 0, - OVL_INFMT_RGB888 = 1, - OVL_INFMT_RGBA8888 = 2, - OVL_INFMT_ARGB8888 = 3, - OVL_INFMT_UYVY = 4, - OVL_INFMT_YUYV = 5, - OVL_INFMT_UNKNOWN = 16, - - OVL_COLOR_BASE = 30, - OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, - OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, - OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, - OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, -}; - void mtk_ddp_init(void); void mtk_ddp_mode_set(const struct edid *edid);
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/mt8183_ddp.c similarity index 63% rename from src/soc/mediatek/mt8183/ddp.c rename to src/soc/mediatek/mt8183/mt8183_ddp.c index d845981..bf8f368 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/mt8183_ddp.c @@ -21,11 +21,9 @@ #include <string.h> #include <stddef.h> #include <soc/addressmap.h> +#include <soc/mt8183_ddp.h> #include <soc/ddp.h>
-#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) -#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) - static void disp_config_main_path_connection(void) { write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); @@ -46,67 +44,11 @@ write32(&disp_mutex->mutex[0].en, BIT(0)); }
-static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) -{ - write32(&disp_ovl[idx]->roi_size, height << 16 | width); - write32(&disp_ovl[idx]->roi_bgclr, color); -} - -static void ovl_layer_enable(u32 idx) -{ - write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); - write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); - - setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); -} - static void ovl_bgclr_in_sel(u32 idx) { setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); }
-static void rdma_start(u32 idx) -{ - setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); -} - -static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh) -{ - u32 threshold; - u32 reg; - u32 fifo_size; - - clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); - clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); - - /* - * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the - * FIFO pseudo size reset default of 8 KiB. Set the output threshold to - * 6 microseconds with 7/6 overhead to account for blanking, and with a - * pixel depth of 4 bytes: - */ - fifo_size = RDMA_FIFO_SIZE_0 * KiB; - - threshold = width * height * vrefresh * 4 * 7 / 1000000; - - if (threshold > fifo_size) - threshold = fifo_size; - - reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(fifo_size) | - RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - - write32(&disp_rdma[idx]->fifo_con, reg); -} - -static void color_start(u32 width, u32 height) -{ - write32(&disp_color->width, width); - write32(&disp_color->height, height); - write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); - write32(&disp_color->start, BIT(0)); -} - static void aal_start(u32 width, u32 height) { write32(&disp_aal->size, height << 16 | width); @@ -133,18 +75,10 @@ write32(&disp_gamma->en, PQ_EN); }
-static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) -{ - write32(&disp_ovl[idx]->layer[0].con, fmt << 12); - write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); - write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); - - ovl_layer_enable(idx); -} - static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) { u32 idx = 0; + u32 pixel_clk = width * height * vrefresh;
/* Setup OVL */ for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { @@ -157,7 +91,7 @@ }
idx = 0; - rdma_config(idx, width, height, vrefresh); + rdma_config(idx, width, height, pixel_clk); color_start(width, height); ccorr_start(width, height); aal_start(width, height);