Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45336 )
Change subject: soc/intel/common/pch: Add Intel common reset code ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45336/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45336/2//COMMIT_MSG@13 PS2, Line 13: TEST=Able to boot CML and TGL platform. Are you able to reset them too? 😊
https://review.coreboot.org/c/coreboot/+/45336/2/src/soc/intel/common/pch/re... File src/soc/intel/common/pch/reset/reset.c:
https://review.coreboot.org/c/coreboot/+/45336/2/src/soc/intel/common/pch/re... PS2, Line 14: * BIOS should ensure it does a global reset : * to reset both host and Intel ME by setting : * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] : */ 96 chars wide on new files
https://review.coreboot.org/c/coreboot/+/45336/2/src/soc/intel/common/pch/re... PS2, Line 20: /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port : * to global reset platform */ same here
https://review.coreboot.org/c/coreboot/+/45336/2/src/soc/intel/common/pch/re... PS2, Line 28: /* If ME unable to reset platform then : * force global reset using PMC CF9GR register*/ same