Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12614
-gerrit
commit f32f60cd74ebb070d726b54cf58a39d1e2850007 Author: Jimmy Huang jimmy.huang@mediatek.com Date: Fri Jul 31 17:10:50 2015 +0800
google/oak: Add MMU support
BRANCH=none BUG=none TEST=build pass
Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang jimmy.huang@mediatek.com Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin yidi.lin@mediatek.com Original-Tested-by: Yidi Lin yidi.lin@mediatek.com Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/mainboard/google/oak/romstage.c | 5 ++ src/soc/mediatek/mt8173/Makefile.inc | 2 + src/soc/mediatek/mt8173/bootblock.c | 3 + .../mediatek/mt8173/include/soc/mmu_operations.h | 39 ++++++++++++ src/soc/mediatek/mt8173/mmu_operations.c | 72 ++++++++++++++++++++++ 5 files changed, 121 insertions(+)
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index ce736e4..354e876 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -20,6 +20,7 @@ #include <arch/cpu.h> #include <arch/exception.h> #include <arch/io.h> +#include <arch/mmu.h>
#include <cbfs.h> #include <console/console.h> @@ -29,6 +30,8 @@ #include <symbols.h> #include <timestamp.h>
+#include <soc/mmu_operations.h> + void main(void) { timestamp_add_now(TS_START_ROMSTAGE); @@ -37,5 +40,7 @@ void main(void) console_init(); exception_init();
+ mt8173_mmu_after_dram(); + run_ramstage(); } diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 4321989..e29154b 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -31,6 +31,7 @@ endif
bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += wdt.c +bootblock-y += mmu_operations.c
################################################################################
@@ -51,6 +52,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c romstage-y += spi.c romstage-y += gpio.c +romstage-y += mmu_operations.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index b284dd0..cd951a8 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -18,6 +18,7 @@ */
#include <bootblock_common.h> +#include <soc/mmu_operations.h> #include <soc/mt6391.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -32,6 +33,8 @@ void bootblock_soc_init(void) /* post init pll */ mt_pll_post_init();
+ mt8173_mmu_init(); + /* init watch dog, will disable AP watch dog */ mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h new file mode 100644 index 0000000..82393f9 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ +#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ + +#include <arch/mmu.h> + +enum { + DEV_MEM = MA_DEV | MA_S | MA_RW, + CACHED_MEM = MA_MEM | MA_NS | MA_RW, + SECURE_MEM = MA_MEM | MA_S | MA_RW, + UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, +}; + +extern unsigned char _sram_l2c[]; +extern unsigned char _esram_l2c[]; +#define _sram_l2c_size (_esram_l2c - _sram_l2c) + +void mt8173_mmu_init(void); +void mt8173_mmu_after_dram(void); + +#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c new file mode 100644 index 0000000..5d3a8d8 --- /dev/null +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <console/console.h> +#include <symbols.h> +#include <stdlib.h> +#include <stdint.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB; + +void mt8173_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to end of dram as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + dram_size, DEV_MEM); + + /* SRAM is cached */ + mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); + + /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + + /* set ttb as secure */ + mmu_config_range(_ttb, _ttb_size, SECURE_MEM); + + mmu_enable(); +} + +void mt8173_mmu_after_dram(void) +{ + /* Remap DRAM as cached now that it's up and running */ + mmu_config_range(_dram, dram_size, CACHED_MEM); + + /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ + /* TODO: Implement true unmapping, and also use it for the zero-page! */ + mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + + /* Careful: changing cache geometry while it's active is a bad idea! */ + mmu_disable(); + + /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max + * available L2 cache for A53 in MT8173. */ + write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8); + /* turn off the l2c sram clock */ + write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN); + + /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + mmu_enable(); +}