[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/amd/common: Use configure_scimap()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43012 )

Change subject: [WIP] soc/amd/common: Use configure_scimap()
......................................................................

[WIP] soc/amd/common: Use configure_scimap()

There is little point stashing the SCI trigger register
configuration. Remove it to mase SCI and SMI programming
more symmetrical.

Change-Id: Ie23da79546858282910db65182a6315ade506279
Signed-off-by: Kyösti Mälkki 
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 12 insertions(+), 36 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43012/1

diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 1bcfc8b..141d04f 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -40,12 +40,6 @@
    configure_gevent_smi(gevent_num, SMI_MODE_SMI, level);
 }

-struct sci_trigger_regs {
-	uint32_t mask;
-	uint32_t polarity;
-	uint32_t level;
-};
-
 /*
  * For each general purpose event, GPE, the choice of edge/level triggered
  * event is represented as a single bit in SMI_SCI_LEVEL register.
@@ -53,37 +47,24 @@
  * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is
  * represented as a single bit in SMI_SCI_TRIG register.
  */
-static void fill_sci_trigger(uint32_t flags, int gpe, struct sci_trigger_regs *regs)
+static void program_sci(uint32_t flags, int gevent_num)
 {
-	uint32_t mask = 1 << gpe;
+	struct sci_source sci;

-	regs->mask |= mask;
+	sci.scimap = gevent_num;
+	sci.gpe = gevent_num;

if (is_gpio_event_level_triggered(flags))
-		regs->level |= mask;
+		sci.level = SMI_SCI_LVL;
    else
-		regs->level &= ~mask;
+		sci.level = SMI_SCI_EDG;

if (is_gpio_event_active_high(flags))
-		regs->polarity |= mask;
+		sci.direction = SMI_SCI_LVL_HIGH;
    else
-		regs->polarity &= ~mask;
-}
+		sci.direction = SMI_SCI_LVL_LOW;

-/* TODO: See configure_scimap() implementations. */
-static void set_sci_trigger(const struct sci_trigger_regs *regs)
-{
-	uint32_t value;
-
-	value = smi_read32(SMI_SCI_TRIG);
-	value &= ~regs->mask;
-	value |= regs->polarity;
-	smi_write32(SMI_SCI_TRIG, value);
-
-	value = smi_read32(SMI_SCI_LEVEL);
-	value &= ~regs->mask;
-	value |= regs->level;
-	smi_write32(SMI_SCI_LEVEL, value);
+	configure_scimap(&sci);
 }

uintptr_t gpio_get_address(gpio_t gpio_num)
@@ -175,7 +156,7 @@

__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {}

-static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg)
+static void set_single_gpio(const struct soc_amd_gpio *g)
 {
    static const struct soc_amd_event *gev_tbl;
    static size_t gev_items;
@@ -206,14 +187,12 @@
    if (g->flags & GPIO_FLAG_SMI) {
    	program_smi(g->flags, gevent_num);
    } else if (g->flags & GPIO_FLAG_SCI) {
-		fill_sci_trigger(g->flags, gevent_num, sci_cfg);
-		soc_route_sci(gevent_num);
+		program_sci(g->flags, gevent_num);
    }
 }

void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 {
-	struct sci_trigger_regs sci_trigger_cfg = { 0 };
    size_t i;

/*
@@ -229,7 +208,7 @@
    master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);

for (i = 0; i < size; i++)
-		set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg);
+		set_single_gpio(&gpio_list_ptr[i]);

/*
     * Re-enable interrupt status generation.
@@ -239,9 +218,6 @@
     * to be missed during boot.
     */
    master_switch_set(GPIO_INTERRUPT_EN);
-
-	/* Set all SCI trigger polarity (high/low) and level (edge/level). */
-	set_sci_trigger(&sci_trigger_cfg);
 }

int gpio_interrupt_status(gpio_t gpio)