Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 )
Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/irq/irq.c:
https://review.coreboot.org/c/coreboot/+/51159/comment/06e0b6df_ed412508 PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ This is tying a knot in my head... it can only be true for devices that still use PIRQs and for devices that can be configured we don't take this into account (we actually ignore it and use find_global_least_used_pirq(), right?). Maybe it's like this:
if (16 <= entries[i].irq && entries[i].irq <= 23) pin_irq_map[num_devs].pic_pirq = (enum pirq)entries[i].irq - 16; else /* dooooooom */;
Really not sure about the else case. My theory: If a device uses a unique IRQ, it just can't work in legacy PIC mode; if it would use a PIRQ in legacy PIC mode, how would it know when that is the case?
Maybe it's time to throw it all* away? (*legacy PIC for ACPI aware OSs) Has anybody used that in the past 10..20 years?