[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Andrey Petrov, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39625

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
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soc/intel/xeon_sp: Modify FSP-T code caching parameters

Added variable CONFIG_BIOS_REGION_SIZE for this purpose.

Tested on OCP Tioga Pass.

Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/bootblock/bootblock.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39625/2