Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48738 )
Change subject: soc/intel/xeon_sp/cpx: Disable ISOC via UPD to improve MLC performance ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48738/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48738/2//COMMIT_MSG@7 PS2, Line 7: soc/intel/xeon_sp/cpx: Disable ISOC via UPD to improve MLC performance Even I find this commit message hard to understand. I would rewrite it as follows:
soc/intel/xeon_sp/cpx: Disable isoch operation for performance
Isochronous operation negatively impacts memory performance, as per Intel MLC (Memory Latency Checker) benchmark results. Thus, disable isochronous operation, like analogous UEFI firmware does.
TEST=On OCP Delta Lake, verify that MLC benchmark results have improved and are now on par with analogous UEFI firmware.
https://review.coreboot.org/c/coreboot/+/48738/2//COMMIT_MSG@13 PS2, Line 13: with UEFI BIOS.
What utility is used for the test?
MLC (memory latency checker) is the tool used for testing, but I had to look it up.
https://review.coreboot.org/c/coreboot/+/48738/2/src/soc/intel/xeon_sp/cpx/r... File src/soc/intel/xeon_sp/cpx/romstage.c:
https://review.coreboot.org/c/coreboot/+/48738/2/src/soc/intel/xeon_sp/cpx/r... PS2, Line 166: Disable ISOC Consider mentioning why, e.g.: `Disable isochronous operation to improve performance`