Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42563 )
Change subject: [RFC] AMD APM_CNT and SMI enablement ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42563/1/src/soc/amd/picasso/southbr... File src/soc/amd/picasso/southbridge.c:
https://review.coreboot.org/c/coreboot/+/42563/1/src/soc/amd/picasso/southbr... PS1, Line 238: * ACPI tables are generated. Enable these ports indiscriminately. The link of CB:42377 doesn't resolve to anything for me. Oh, you must mean in the case where the write fails to trigger the SMI and the APM_CNT isn't serviced.
This should possibly happen right after PARALLEL_MP
I agree.
...or even before SMM relocation runs.
I would probably do it after. The relocation happens as part of mp_init_with_smm() so that call should ensure APM_CNT isn't used or required until it completes. mp_init_with_smm() takes struct mp_ops and has a .post_mp_init that looks like the right place to program the address.
PARALLEL_MP raises SMI via lapic?
Right. You should be able to find smm_initiate_relocation_parallel() in mp_init.c and see the LAPIC write there.