Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33624 )
Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/33624/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33624/9//COMMIT_MSG@9 PS9, Line 9: carrizo CPU in a SOC presentation
I would prefer you don't mention this. […]
Ok, will do.
https://review.coreboot.org/c/coreboot/+/33624/9//COMMIT_MSG@12 PS9, Line 12: merlinfalcon
You also might want to develop the habit of capitalizing the first letters of codenames, e.g. […]
I was not sure if Merlin Falcon was a single word or 2 words (which looks better). Will do.
https://review.coreboot.org/c/coreboot/+/33624/9/src/soc/amd/stoneyridge/chi... File src/soc/amd/stoneyridge/chip.h:
https://review.coreboot.org/c/coreboot/+/33624/9/src/soc/amd/stoneyridge/chi... PS9, Line 29: MAX_DIMMS_PER_CH
Are you certain of this? Can you direct me to the document? I only see 2 DIMMs in the BKDG. […]
I got it from Marc's code. I have no documentation to say either way. It's probably due to 4 cores against stoney's 2 cores.