Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63544 )
Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ......................................................................
mb/google/brask/variants/moli: add delay time to rtd3-cold
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing.
We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:228907551 TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi raihow_shi@wistron.corp-partner.google.com Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 5d17976..e9bc846 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -100,6 +100,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "srcclk_pin" = "1" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1 register "pch_pcie_rp[PCH_RP(12)]" = "{
9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.