Varad (varadgautam@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8631
-gerrit
commit 0a3073134dc86b8dc344c3a94d86e3dedda022e0 Author: Varad Gautam varadgautam@gmail.com Date: Sun Mar 8 23:10:21 2015 +0530
global: Refactor get_option usage
Assign option to its default value to avoid checking what get_option returns.
Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam varadgautam@gmail.com --- src/console/init.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 4 ++-- src/mainboard/ibase/mb899/superio_hwm.c | 26 +++++++++++++------------- src/mainboard/kontron/986lcd-m/mainboard.c | 26 +++++++++++++------------- src/northbridge/amd/amdk8/misc_control.c | 4 ++-- src/southbridge/amd/sb600/sata.c | 6 ++---- src/southbridge/intel/i82801dx/lpc.c | 4 ++-- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- 9 files changed, 40 insertions(+), 42 deletions(-)
diff --git a/src/console/init.c b/src/console/init.c index e638216..1fbe22a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -37,8 +37,8 @@ int console_log_level(int msg_level) void console_init(void) { #if !defined(__PRE_RAM__) - if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) - console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + get_option(&console_loglevel, "debug_level"); #endif
#if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 341bb62..d33f4bb 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -251,8 +251,8 @@ static void init_ecc_memory(unsigned node_id)
/* See if we scrubbing should be enabled */ enable_scrubbing = 1; - if (get_option(&enable_scrubbing, "hw_scrubber") != CB_SUCCESS) - enable_scrubbing = CONFIG_HW_SCRUBBER; + enable_scrubbing = CONFIG_HW_SCRUBBER; + get_option(&enable_scrubbing, "hw_scrubber");
/* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7864264..4c7d123 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -80,19 +80,19 @@ void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0;
- if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature");
// hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..d943127 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -79,19 +79,19 @@ static void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0;
- if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature");
// hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 956692d..d4747fd 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -48,8 +48,8 @@ static void mcf3_read_resources(device_t dev) }
iommu = 1; - if (get_option(&iommu, "iommu") != CB_SUCCESS) - iommu = CONFIG_IOMMU; + iommu = CONFIG_IOMMU; + get_option(&iommu, "iommu");
if (iommu) { /* Add a GART aperture resource */ diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 2ff7182..34ac0ac 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -119,10 +119,8 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x40, byte);
// 1 means IDE, 0 means AHCI - if (get_option(&i, "sata_mode") != CB_SUCCESS) { - // no cmos option - i = CONFIG_SATA_MODE; - } + i = CONFIG_SATA_MODE; + get_option(&i, "sata_mode"); printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );
dword = pci_read_config32(dev, 0x8); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 83d6178..2f3db86 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -116,8 +116,8 @@ static void i82801dx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail");
reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index cbc0106..b8edfe3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -179,8 +179,8 @@ static void i82801gx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail");
reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0ba33d6..4f576c4 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -186,8 +186,8 @@ static void i82801ix_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail");
reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe;