Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48517 )
Change subject: soc/amd/cezanne: add caching setup in bootblock ......................................................................
Patch Set 2: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/48517/2/src/soc/amd/cezanne/bootblo... File src/soc/amd/cezanne/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48517/2/src/soc/amd/cezanne/bootblo... PS2, Line 59: ALIGN_DOWN(top_mem.lo, 8*MiB)
i'm not sure what should only work when it's a power of 2. the second parameter of ALIGN_DOWN is a power of two and the parameter of var_mtrr_set doesn't seem to need to be a power of 2.
My bad. The name looks a lot like set_var_mtrr which has this requirement.
https://review.coreboot.org/c/coreboot/+/48517/2/src/soc/amd/cezanne/bootblo... PS2, Line 60: CONFIG_ROM_SIZE
the symbols needed by CAR_CACHE_ROM_SIZE are likely not available, since this soc doesn't use CAR. I also haven't seen a non power of two flash configuration on AMD like there might be on Intel systems. from the datasheet, i'd expect this region to always be 16MByte
Sry, I was confused with set_var_mtrr().