Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32992 )
Change subject: soc/intel/cannonlake: Add ability to disable Heci1 ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/chip.h@424 PS5, Line 424: Heci1Disabled
make use of config HeciEnabled line 218
Done
https://review.coreboot.org/#/c/32992/4/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/#/c/32992/4/src/soc/intel/cannonlake/chip.h@216 PS4, Line 216: /* HeciEnabled decides the state of Heci1 at end of boot : * Setting to 0 (default) disables Heci1 and hides the device from OS */ : uint8_t HeciEnabled;
CL https://review.coreboot. […]
Done
https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/fsp_params.... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/#/c/32992/5/src/soc/intel/cannonlake/fsp_params.... PS5, Line 344: Heci1Disabled
i guess you can use !config->HeciEnabled to assign FSP UPD, in that way you don't need another one
Done