[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/common/block/lpc: Limit ROM2 to 16MiB

[Maximilian Brune (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph.

Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86582?usp=email )

Change subject: soc/amd/common/block/lpc: Limit ROM2 to 16MiB
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Patch Set 1:

(2 comments)

File src/soc/amd/common/block/lpc/lpc_util.c:

https://review.coreboot.org/c/coreboot/+/86582/comment/7f3ac32c_ad4f9ec8?usp... :
PS1, Line 280: if (CONFIG_COREBOOT_ROMSIZE_KB <= 16384)
nit:
add comment like:
```
limit the mapping to a maximum of 16MiB.
```

https://review.coreboot.org/c/coreboot/+/86582/comment/ce4234bc_49441020?usp... :
PS1, Line 284: 		pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0xff00);
nit:
I guess you could also write:
```
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 - (MIN(CONFIG_COREBOOT_ROMSIZE_KB, 16384) >> 6));
```