Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21280
Change subject: soc/intel/cannonlake: Add Vboot/ChromOS support ......................................................................
soc/intel/cannonlake: Add Vboot/ChromOS support
Add Vboot and Chromeos support in SOC Kconfig, include a seperated verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 2 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21280/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ac15742..9c94cbd6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -119,4 +119,16 @@ hex default 0xc35
+config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index facbd22..000522c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,12 @@ bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c
+verstage-y += gspi.c +verstage-$(CONFIG_UART_DEBUG) += uart.c +verstage-y += pmutil.c +verstage-y += spi.c + +romstage-y += gpio.c romstage-y += gspi.c romstage-y += memmap.c romstage-y += pmutil.c