Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43792 )
Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur ......................................................................
mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms.
Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo.
Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya v.sowmya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Sridhar Siricilla sridhar.siricilla@intel.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Ronak Kanabar: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d0609ef..e7c5656 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -166,6 +166,20 @@ # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1"
+ # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device