[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41674 )

Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41674/4/src/soc/intel/common/block/... 
File src/soc/intel/common/block/sata/sata.c:

https://review.coreboot.org/c/coreboot/+/41674/4/src/soc/intel/common/block/... 
PS4, Line 12: #define SATA_PCI_CFG_PORT_CTL_STS	0x92
> > This changed to 0x94 with Cannon Point PCH. […]

coreboot never set SPD bits on purpose for these FSP platforms. Please
confirm if it's coreboot's or FSP's responsibility to set those. If you
are unsure, just dump the register state after FSP-S run and check if
it already handles things. If it does, we can disable this driver for
all platforms that we tested positively without it.