Hello Kyösti Mälkki,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34995
to review the following change.
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
arch/x86: Cache the TSEG region at the top of ram
This patch helps to save additional ~6ms of booting time in normal and s3 resume on CML-hatch.
Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/arch/x86/postcar_loader.c 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/1
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index bceed6c..408d155 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -20,6 +20,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <program_loading.h> #include <rmodule.h> #include <romstage_handoff.h> @@ -149,6 +150,23 @@ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); }
+/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +static void enable_tseg_cache(struct postcar_frame *pcf) +{ + uintptr_t smm_base; + size_t smm_size; + + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, + MTRR_TYPE_WRBACK); +} + void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { @@ -159,6 +177,9 @@ */ if (!acpi_is_wakeup_s3()) enable_top_of_dram_cache(addr, size); + + enable_tseg_cache(pcf); + postcar_frame_add_mtrr(pcf, addr, size, type); }