build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38490 )
Change subject: soc/mediatek/mt8183: improve the DRAMC runtime config flow ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 493: (0x1 << 6) | (0x1 << 4)| (0x1 << 2), need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/emi... PS1, Line 329: [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, .rfrc_pb05t = 0, .tx_ref_cnt = 62}, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/emi... PS1, Line 330: [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, .rfrc_pb05t = 0, .tx_ref_cnt = 91}, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/emi... PS1, Line 331: [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, .rfrc_pb05t = 0, .tx_ref_cnt = 119}, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/emi... PS1, Line 332: [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, .rfrc_pb05t = 1, .tx_ref_cnt = 138}, line over 96 characters