Caesar Wang has uploaded a new change for review. ( https://review.coreboot.org/19557 )
Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ......................................................................
rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
Spread Spectrum Modulator(SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI.
We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng zhengxing@rock-chips.com Signed-off-by: Caesar Wang wxt@rock-chips.com --- M src/mainboard/google/gru/Kconfig M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/clock.c 3 files changed, 67 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/1
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 0fce7cc..0dba3e9 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -38,6 +38,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select RAM_CODE_SUPPORT + select RK3399_SPREAD_SPECTRUM_DDR if BOARD_GOOGLE_BOB select RTC select SOC_ROCKCHIP_RK3399 select SPI_FLASH diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 65b31d5..c2bb7cc 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -24,4 +24,9 @@ int default -1
+config RK3399_SPREAD_SPECTRUM_DDR + bool "Build for a board revision with ddr ssc" + default n + default y if BOARD_GOOGLE_BOB + endif diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index eb413a1..ef70c1b 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -82,7 +82,22 @@ PLL_MODE_DEEP, PLL_DSMPD_MASK = 1, PLL_DSMPD_SHIFT = 3, + PLL_FRAC_MODE = 0, PLL_INTEGER_MODE = 1, + + /* PLL_CON4 */ + PLL_SSMOD_BP_MASK = 1, + PLL_SSMOD_BP_SHIFT = 0, + PLL_SSMOD_DIS_SSCG_MASK = 1, + PLL_SSMOD_DIS_SSCG_SHIFT = 1, + PLL_SSMOD_RESET_MASK = 1, + PLL_SSMOD_RESET_SHIFT = 2, + PLL_SSMOD_DOWNSPEAD_MASK = 1, + PLL_SSMOD_DOWNSPEAD_SHIFT = 3, + PLL_SSMOD_DIVVAL_MASK = 0Xf, + PLL_SSMOD_DIVVAL_SHIFT = 4, + PLL_SSMOD_SPREADAMP_MASK = 0x1f, + PLL_SSMOD_SPREADAMP_SHIFT = 8,
/* PMUCRU_CLKSEL_CON0 */ PMU_PCLK_DIV_CON_MASK = 0x1f, @@ -325,6 +340,47 @@ write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, PLL_MODE_NORM << PLL_MODE_SHIFT)); } + +#if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) + +/* Configure the DPLL spread spectrum feature on memory clock. */ +static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) +{ + u32 divval; + + /* Need to acquire ~30kHZ which is the target modulation frequency. + * The modulation frequency ~ 30kHz= OSC_HZ/revdiv/128/divval + * (the 128 is the number points in the query table). + */ + assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); + divval = OSC_HZ / 128 / (30 * KHz) / dpll_cfg->refdiv; + + /* use frac mode */ + write32(&cru_ptr->dpll_con[3], + RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, + PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); + + /* enable SSC for DPLL */ + write32(&cru_ptr->dpll_con[4], + RK_CLRBITS(PLL_SSMOD_BP_MASK << PLL_SSMOD_BP_SHIFT | + PLL_SSMOD_DIS_SSCG_MASK << PLL_SSMOD_DIS_SSCG_SHIFT | + PLL_SSMOD_RESET_MASK << PLL_SSMOD_RESET_SHIFT)); + + /* set SSC divval */ + write32(&cru_ptr->dpll_con[4], + RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, + divval << PLL_SSMOD_DIVVAL_SHIFT)); + + /* set SSC amplitude, + * SSMOD SPREADAMP value 8 appears to mitigate EMI on boards tested. + */ + write32(&cru_ptr->dpll_con[4], + RK_CLRSETBITS(PLL_SSMOD_SPREADAMP_MASK << + PLL_SSMOD_SPREADAMP_SHIFT, + 8 << PLL_SSMOD_SPREADAMP_SHIFT)); +} + +#endif
static int pll_para_config(u32 freq_hz, struct pll_div *div) { @@ -571,6 +627,11 @@ die("Unsupported SDRAM frequency, add to clock.c!"); } rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); + +#if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) + /* configure DPLL SSC */ + rkclk_set_dpllssc(&dpll_cfg); +#endif }
#define SPI_CLK_REG_VALUE(bus, clk_div) \