[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Andrey Petrov, Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39625

to look at the new patch set (#6).

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
......................................................................

soc/intel/xeon_sp: Modify FSP-T code caching parameters

Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching
parameters.

Tested on OCP Tioga Pass.

Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/bootblock/bootblock.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39625/6