[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 142: 	set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
> Thinking about it, setting MTRRs might have only an effect if CQOS NEM is used. […]

i don't think its anything specific to NEM enhance or CQOS. Its in general NEM mode thing as i understood.