[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Read spds only once if measured boot is enabled

[Bill XIE (Code Review)]

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39969 )

Change subject: nb/intel/sandybridge: Read spds only once if measured boot is enabled
......................................................................

nb/intel/sandybridge: Read spds only once if measured boot is enabled

Without considering s3 resume, spd may be used various times depending
on various condition. If spd is stored in CBFS and read various times,
PCR value may become inconsistent.

As mentioned in CB:39906, in order to avoid this, we could read spd
exactly once, and use the data read out various times, when measured
boot is enabled.

Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233
Signed-off-by: Bill XIE 
---
M src/northbridge/intel/sandybridge/raminit.c
1 file changed, 27 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39969/1

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b096a11..f3c81a6 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -98,6 +98,17 @@
    }
 }

+static bool spd_is_available(const spd_raw_data spds[], size_t num_spd)
+{
+	/* An available spd should at least have an non-zero id */
+	size_t i, j, sum = 0;
+	for (i = 0; i < num_spd; i++) {
+		for (j = 117; j < 128; j++)
+			sum += spds[i][j];
+	}
+	return (sum > 0);
+}
+
 static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
 {
    int dimms = 0, ch_dimms;
@@ -222,6 +233,8 @@
    struct region_device rdev;
    ramctr_timing *ctrl_cached = NULL;

+	if (CONFIG(TPM_MEASURED_BOOT))
+		memset(spds, 0, sizeof(spds));
    MCHBAR32(SAPMCTL) |= 1;

/* Wait for ME to be ready */
@@ -271,8 +284,14 @@
    /* Verify MRC cache for fast boot */
    if (!s3resume && ctrl_cached) {
    	/* Load SPD unique information data. */
-		memset(spds, 0, sizeof(spds));
-		mainboard_get_spd(spds, 1);
+		if (CONFIG(TPM_MEASURED_BOOT)) {
+			/* if CONFIG(TPM_MEASURED_BOOT),
+			   we manage to get spds only ONCE */
+			mainboard_get_spd(spds, 0);
+		} else {
+			memset(spds, 0, sizeof(spds));
+			mainboard_get_spd(spds, 1);
+		}

/* check SPD CRC16 to make sure the DIMMs haven't been replaced */
    	fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached);
@@ -307,8 +326,12 @@
    	ctrl.cpu = cpuid;

/* Get DDR3 SPD data */
-		memset(spds, 0, sizeof(spds));
-		mainboard_get_spd(spds, 0);
+		if (!CONFIG(TPM_MEASURED_BOOT) || !spd_is_available(spds, 4)) {
+			/* without CONFIG(TPM_MEASURED_BOOT), the previous read may
+			   only contains id, so read it again */
+			memset(spds, 0, sizeof(spds));
+			mainboard_get_spd(spds, 0);
+		}
    	dram_find_spds_ddr3(spds, &ctrl);

err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);