Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8406
-gerrit
commit 771a427b10318e93d707ace0acfc35c493f37497 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Tue Feb 10 21:22:36 2015 +0100
Drop Intel E7501 / i82801ex and Tyan s2735
Change-Id: I0830d0f54189e855ef14b0d84bed74ba41b84efb Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/mainboard/tyan/Kconfig | 3 - src/mainboard/tyan/s2735/Kconfig | 41 - src/mainboard/tyan/s2735/board_info.txt | 3 - src/mainboard/tyan/s2735/cmos.layout | 82 -- src/mainboard/tyan/s2735/devicetree.cb | 86 -- src/mainboard/tyan/s2735/irq_tables.c | 45 - src/mainboard/tyan/s2735/mptable.c | 130 -- src/mainboard/tyan/s2735/romstage.c | 76 - src/northbridge/intel/Kconfig | 1 - src/northbridge/intel/Makefile.inc | 1 - src/northbridge/intel/e7501/Kconfig | 5 - src/northbridge/intel/e7501/Makefile.inc | 1 - src/northbridge/intel/e7501/debug.c | 275 ---- src/northbridge/intel/e7501/e7501.h | 79 - src/northbridge/intel/e7501/northbridge.c | 140 -- src/northbridge/intel/e7501/raminit.c | 2007 -------------------------- src/northbridge/intel/e7501/raminit.h | 20 - src/northbridge/intel/e7501/reset_test.c | 18 - src/southbridge/intel/Kconfig | 1 - src/southbridge/intel/Makefile.inc | 1 - src/southbridge/intel/i82801ex/Kconfig | 14 - src/southbridge/intel/i82801ex/Makefile.inc | 11 - src/southbridge/intel/i82801ex/ac97.c | 37 - src/southbridge/intel/i82801ex/chip.h | 34 - src/southbridge/intel/i82801ex/early_smbus.c | 130 -- src/southbridge/intel/i82801ex/ehci.c | 51 - src/southbridge/intel/i82801ex/i82801ex.c | 48 - src/southbridge/intel/i82801ex/i82801ex.h | 22 - src/southbridge/intel/i82801ex/ide.c | 42 - src/southbridge/intel/i82801ex/lpc.c | 381 ----- src/southbridge/intel/i82801ex/pci.c | 44 - src/southbridge/intel/i82801ex/reset.c | 8 - src/southbridge/intel/i82801ex/sata.c | 59 - src/southbridge/intel/i82801ex/smbus.c | 48 - src/southbridge/intel/i82801ex/smbus.h | 104 -- src/southbridge/intel/i82801ex/uhci.c | 55 - src/southbridge/intel/i82801ex/watchdog.c | 28 - 37 files changed, 4131 deletions(-)
diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig index 4a135bd..fb16996 100644 --- a/src/mainboard/tyan/Kconfig +++ b/src/mainboard/tyan/Kconfig @@ -23,8 +23,6 @@ choice
config BOARD_TYAN_S1846 bool "S1846 (Tsunami ATX)" -config BOARD_TYAN_S2735 - bool "S2735 (Tiger i7501R)" config BOARD_TYAN_S2850 bool "S2850 (Tomcat K8S)" config BOARD_TYAN_S2875 @@ -56,7 +54,6 @@ config BOARD_TYAN_S8226 endchoice
source "src/mainboard/tyan/s1846/Kconfig" -source "src/mainboard/tyan/s2735/Kconfig" source "src/mainboard/tyan/s2850/Kconfig" source "src/mainboard/tyan/s2875/Kconfig" source "src/mainboard/tyan/s2880/Kconfig" diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig deleted file mode 100644 index a64c0e3..0000000 --- a/src/mainboard/tyan/s2735/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -if BOARD_TYAN_S2735 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7501 - select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801EX - select SUPERIO_WINBOND_W83627HF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select UDELAY_TSC - select HAVE_OPTION_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default tyan/s2735 - -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - -config MAINBOARD_PART_NUMBER - string - default "S2735" - -config IRQ_SLOT_COUNT - int - default 15 - -config MAX_CPUS - int - default 4 - -endif # BOARD_TYAN_S2735 diff --git a/src/mainboard/tyan/s2735/board_info.txt b/src/mainboard/tyan/s2735/board_info.txt deleted file mode 100644 index 3eb1393..0000000 --- a/src/mainboard/tyan/s2735/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board name: Tiger i7501R (S2735) -Category: server -Board URL: http://www.tyan.com/archive/products/html/tigeri7501r.html diff --git a/src/mainboard/tyan/s2735/cmos.layout b/src/mainboard/tyan/s2735/cmos.layout deleted file mode 100644 index 58585a2..0000000 --- a/src/mainboard/tyan/s2735/cmos.layout +++ /dev/null @@ -1,82 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -396 1 e 1 thermal_monitoring -397 1 e 1 remap_memory_high -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -#440 4 e 9 slow_cpu -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb deleted file mode 100644 index d3b6b1e..0000000 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ /dev/null @@ -1,86 +0,0 @@ -chip northbridge/intel/e7501 - device domain 0 on - subsystemid 0x10f1 0x2735 inherit - device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 on end - device pci 1d.0 on - device pci 1.0 on end # intel lan - device pci 1.1 on end - end - device pci 1e.0 on end - device pci 1f.0 on end - end - end - device pci 6.0 on end - chip southbridge/intel/i82801ex - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on - device pci 1.0 on end # intel lan 10/100 - device pci 2.0 on end # ati - end - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - end # SB - end # PCI domain - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA604 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 - device lapic 6 on end - end - end -end - diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c deleted file mode 100644 index 3d69b49..0000000 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x24d0, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x04,(0x08<<3)|0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x1d<<3)|0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x0, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x02<<3)|0x0, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x03,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x02,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x03,(0x03<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x1, 0x0}, - {0x03,(0x06<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x2, 0x0}, - {0x02,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x02,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x04,(0x01<<3)|0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0x0dcf8}}, 0x4, 0x0}, - {0x03,(0x04<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x03,(0x05<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x6, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c deleted file mode 100644 index 9073728..0000000 --- a/src/mainboard/tyan/s2735/mptable.c +++ /dev/null @@ -1,130 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - mptable_write_buses(mc, NULL, &isa_bus); -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x09, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x0a, 0x20, res->base); - } - } - } - mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ -//USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17); - -//onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12); - -//onboard intel 82551 10/100 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11); - -// onboard Intel 82547 1000 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1); - -//Slot 4 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11); -//Slot 3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12); -//Slot 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3); -//Slot 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, 0x0); -/* -MP Config Extended Table Entries: - --- -System Address Space - bus ID: 0 address type: I/O address - address base: 0x9000 - address range: 0x6000 --- -System Address Space - bus ID: 0 address type: I/O address - address base: 0x0 - address range: 0x100 --- -System Address Space - bus ID: 0 address type: memory address - address base: 0xa0000 - address range: 0x20000 --- -System Address Space - bus ID: 0 address type: memory address - address base: 0xfc700000 - address range: 0x2500000 --- -System Address Space - bus ID: 0 address type: prefetch address - address base: 0xff600000 - address range: 0x500000 --- -Bus Heirarchy - bus ID: 5 bus info: 0x01 parent bus ID: 0-- -Compatibility Bus Address - bus ID: 0 address modifier: add - predefined range: 0x00000000-- -Compatibility Bus Address - bus ID: 0 address modifier: add - predefined range: 0x00000001 // There is no extension information... -*/ - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c deleted file mode 100644 index 5d4fd0e..0000000 --- a/src/mainboard/tyan/s2735/romstage.c +++ /dev/null @@ -1,76 +0,0 @@ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <lib.h> -#include <spd.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7501/raminit.h" -#include "northbridge/intel/e7501/debug.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -// FIXME: There's another hard_reset() in reset.c. Why? -static void hard_reset(void) -{ - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7501/raminit.c" -#include "northbridge/intel/e7501/reset_test.c" -#include "lib/generic_sdram.c" - -#include <cpu/intel/romstage.h> -void main(unsigned long bist) -{ - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, - .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, - }, - }; - - if (bist == 0) - enable_lapic(); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (bios_reset_detected()) - hard_reset(); - - enable_smbus(); -#if 0 - dump_spd_registers(&memctrl[0]); - dump_smbus_registers(); -#endif - - sdram_initialize(1, memctrl); - -#if 0 - dump_pci_devices(); -#endif - -#if 1 - dump_pci_device(PCI_DEV(0, 0, 0)); -#endif -} diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 9ff66d3..b3df67b 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -1,4 +1,3 @@ -source src/northbridge/intel/e7501/Kconfig source src/northbridge/intel/e7505/Kconfig source src/northbridge/intel/e7525/Kconfig source src/northbridge/intel/i3100/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 020caa8..2239675 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -1,4 +1,3 @@ -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100 diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig deleted file mode 100644 index 88c0b45..0000000 --- a/src/northbridge/intel/e7501/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config NORTHBRIDGE_INTEL_E7501 - bool - select HAVE_DEBUG_RAM_SETUP - select PER_DEVICE_ACPI_TABLES - diff --git a/src/northbridge/intel/e7501/Makefile.inc b/src/northbridge/intel/e7501/Makefile.inc deleted file mode 100644 index 23eada5..0000000 --- a/src/northbridge/intel/e7501/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += northbridge.c diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c deleted file mode 100644 index 07f1596..0000000 --- a/src/northbridge/intel/e7501/debug.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * generic debug code, used by mainboard specific romstage.c - * - */ -#if 1 -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static inline void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - - for(i = 0; i < 256; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x:",i); -#else - print_debug("\n"); - print_debug_hex8(i); - print_debug_char(':'); -#endif - } - val = pci_read_config8(dev, i); -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x", val); -#else - print_debug_char(' '); - print_debug_hex8(val); -#endif - } - print_debug("\n"); -} - -static inline void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -static inline void dump_pci_devices_on_bus(unsigned busn) -{ - device_t dev; - for(dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -static inline void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); -#else - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); -#else - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } - } -} -static inline void dump_smbus_registers(void) -{ - unsigned device; - print_debug("\n"); - for(device = 1; device < 0x80; device++) { - int j; - if( smbus_read_byte(device, 0) < 0 ) continue; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "smbus: %02x", device); -#else - print_debug("smbus: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ",j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } -} - -static inline void dump_io_resources(unsigned port) -{ - - int i; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%04x:\n", port); -#else - print_debug_hex16(port); - print_debug(":\n"); -#endif - for(i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x:", i); -#else - print_debug_hex8(i); - print_debug_char(':'); -#endif - } - val = inb(port); -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x",val); -#else - print_debug_char(' '); - print_debug_hex8(val); -#endif - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - port++; - } -} - -static inline void dump_mem(unsigned start, unsigned end) -{ - unsigned i; - print_debug("dump_mem:"); - for(i=start;i<end;i++) { - if((i & 0xf)==0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%08x:", i); -#else - print_debug("\n"); - print_debug_hex32(i); - print_debug(":"); -#endif - } -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); -#else - print_debug(" "); - print_debug_hex8((unsigned char)*((unsigned char *)i)); -#endif - } - print_debug("\n"); - } -#endif diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h deleted file mode 100644 index 1e431b1..0000000 --- a/src/northbridge/intel/e7501/e7501.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * e7501.h: PCI configuration space for the Intel E7501 memory controller - */ - -/************ D0:F0 ************/ -// Register offsets -#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ -#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ -#define DRB_ROW_1 0x61 -#define DRB_ROW_2 0x62 -#define DRB_ROW_3 0x63 -#define DRB_ROW_4 0x64 -#define DRB_ROW_5 0x65 -#define DRB_ROW_6 0x66 -#define DRB_ROW_7 0x67 - -#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ -#define DRT 0x78 /* DRAM Timing register, 32 bit */ -#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ -#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ -#define CKDIS 0x8C /* Clock disable register, 8 bit */ -#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ -#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ -#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ -#define SKPD 0xDE /* Scratchpad register, 16 bit */ -#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ - -// CAS# Latency bits in the DRAM Timing (DRT) register -#define DRT_CAS_2_5 (0<<4) -#define DRT_CAS_2_0 (1<<4) -#define DRT_CAS_MASK (3<<4) - -// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register -#define RAM_COMMAND_NOP (1<<4) -#define RAM_COMMAND_PRECHARGE (2<<4) -#define RAM_COMMAND_MRS (3<<4) -#define RAM_COMMAND_EMRS (4<<4) -#define RAM_COMMAND_CBR (6<<4) -#define RAM_COMMAND_NORMAL (7<<4) - - -// RCOMP Memory Map offsets -// Conjecture based on apparent similarity between E7501 and 855PM -// Intel doc. 252613-003 describes these for 855PM - -#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */ -#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ -#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */ -#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */ -#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */ -#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ - -/************ D0:F1 ************/ -// Register offsets -#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ -#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ -#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ -#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c deleted file mode 100644 index 64bf840..0000000 --- a/src/northbridge/intel/e7501/northbridge.c +++ /dev/null @@ -1,140 +0,0 @@ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <stdlib.h> -#include <string.h> -#include <cbmem.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - -#endif - - -static void pci_domain_set_resources(device_t dev) -{ - device_t mc_dev; - uint32_t pci_tolm; - - pci_tolm = find_pci_tolm(dev->link_list); - mc_dev = dev->link_list->children; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - uint16_t tolm_r, remapbase_r, remaplimit_r; - unsigned long tomk, tolmk; - unsigned long remapbasek, remaplimitk; - int idx; - - /* Get the value of the highest DRB. This tells the end of - * the physical memory. The units are ticks of 64MB - * i.e. 1 means 64MB. - */ - tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16; - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory - * we won't use the remap window. - */ - tolmk = tomk; - remapbasek = 0x3ff << 16; - remaplimitk = 0 << 16; - } - else { - /* The PCI memory hole overlaps memory - * setup the remap window. - */ - /* Find the bottom of the remap window - * is it above 4G? - */ - remapbasek = 4*1024*1024; - if (tomk > remapbasek) { - remapbasek = tomk; - } - /* Find the limit of the remap window */ - remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); - } - /* Write the ram configuration registers, - * preserving the reserved bits. - */ - tolm_r = pci_read_config16(mc_dev, 0xc4); - tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); - - remapbase_r = pci_read_config16(mc_dev, 0xc6); - remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); - - remaplimit_r = pci_read_config16(mc_dev, 0xc8); - remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); - - /* Report the memory regions */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); - if (tomk > 4*1024*1024) { - ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); - } - if (remaplimitk >= remapbasek) { - ram_resource(dev, idx++, remapbasek, - (remaplimitk + 64*1024) - remapbasek); - } - - set_top_of_ram(tolmk * 1024); - } - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_e7501_ops = { - CHIP_NAME("Intel E7501 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c deleted file mode 100644 index 2247a25..0000000 --- a/src/northbridge/intel/e7501/raminit.c +++ /dev/null @@ -1,2007 +0,0 @@ -/* This was originally for the e7500, modified for e7501 - * The primary differences are that 7501 apparently can - * support single channel RAM (i haven't tested), - * CAS1.5 is no longer supported, The ECC scrubber - * now supports a mode to zero RAM and init ECC in one step - * and the undocumented registers at 0x80 require new - * (undocumented) values determined by guesswork and - * comparison w/ OEM BIOS values. - * Steven James 02/06/2003 - */ - -/* converted to C 6/2004 yhlu */ - -#include <assert.h> -#include <spd.h> -#include <sdram_mode.h> -#include <stdlib.h> -#include "e7501.h" - -/*----------------------------------------------------------------------------- -Definitions: ------------------------------------------------------------------------------*/ - -// Uncomment this to enable run-time checking of DIMM parameters -// for dual-channel operation -// Unfortunately the code seems to chew up several K of space. -//#define VALIDATE_DIMM_COMPATIBILITY - -#if CONFIG_DEBUG_RAM_SETUP -#define RAM_DEBUG_MESSAGE(x) print_debug(x) -#define RAM_DEBUG_HEX32(x) print_debug_hex32(x) -#define RAM_DEBUG_HEX8(x) print_debug_hex8(x) -#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) -#else -#define RAM_DEBUG_MESSAGE(x) -#define RAM_DEBUG_HEX32(x) -#define RAM_DEBUG_HEX8(x) -#define DUMPNORTH() -#endif - -#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) -#define SPD_ERROR "Error reading SPD info\n" - -// NOTE: This used to be 0x100000. -// That doesn't work on systems where A20M# is asserted, because -// attempts to access 0x1000NN end up accessing 0x0000NN. -#define RCOMP_MMIO 0x200000 - -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; - -static const uint32_t refresh_frequency[] = { - /* Relative frequency (array value) of each E7501 Refresh Mode Select - * (RMS) value (array index) - * 0 == least frequent refresh (longest interval between refreshes) - * [0] disabled -> 0 - * [1] 15.6 usec -> 2 - * [2] 7.8 usec -> 3 - * [3] 64 usec -> 1 - * [4] reserved -> 0 - * [5] reserved -> 0 - * [6] reserved -> 0 - * [7] 64 clocks -> 4 - */ - 0, 2, 3, 1, 0, 0, 0, 4 -}; - -static const uint32_t refresh_rate_map[] = { - /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode - * Select values (array value) - * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 - * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and - * 64 clock (481 ns) (7) refresh. - * [0] == 15.625 us -> 15.6 us - * [1] == 3.9 us -> 481 ns - * [2] == 7.8 us -> 7.8 us - * [3] == 31.3 us -> 15.6 us - * [4] == 62.5 us -> 15.6 us - * [5] == 125 us -> 64 us - */ - 1, 7, 2, 1, 1, 3 -}; - -#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) - -// SPD parameters that must match for dual-channel operation -static const uint8_t dual_channel_parameters[] = { - SPD_MEMORY_TYPE, - SPD_MODULE_VOLTAGE, - SPD_NUM_COLUMNS, - SPD_NUM_ROWS, - SPD_NUM_DIMM_BANKS, - SPD_PRIMARY_SDRAM_WIDTH, - SPD_NUM_BANKS_PER_SDRAM -}; - - /* - * Table: constant_register_values - */ -static const long constant_register_values[] = { - /* SVID - Subsystem Vendor Identification Register - * 0x2c - 0x2d - * [15:00] Subsytem Vendor ID (Indicates system board vendor) - */ - /* SID - Subsystem Identification Register - * 0x2e - 0x2f - * [15:00] Subsystem ID - */ - // Not everyone wants to be Super Micro Computer, Inc. - // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), - - /* Undocumented - * (DRAM Read Timing Control, if similar to 855PM?) - * 0x80 - 0x81 - * This register has something to do with CAS latencies, - * possibily this is the real chipset control. - * At 0x00 CAS latency 1.5 works. - * At 0x06 CAS latency 2.5 works. - * At 0x01 CAS latency 2.0 works. - */ - /* This is still undocumented in e7501, but with different values - * CAS 2.0 values taken from Intel BIOS settings, others are a guess - * and may be terribly wrong. Old values preserved as comments until I - * figure this out for sure. - * e7501 docs claim that CAS1.5 is unsupported, so it may or may not - * work at all. - * Steven James 02/06/2003 - */ - /* NOTE: values now configured in configure_e7501_cas_latency() based - * on SPD info and total number of DIMMs (per Intel) - */ - - /* FDHC - Fixed DRAM Hole Control - * 0x58 - * [7:7] Hole_Enable - * 0 == No memory Hole - * 1 == Memory Hole from 15MB to 16MB - * [6:0] Reserved - * - * PAM - Programmable Attribute Map - * 0x59 [1:0] Reserved - * 0x59 [5:4] 0xF0000 - 0xFFFFF - * 0x5A [1:0] 0xC0000 - 0xC3FFF - * 0x5A [5:4] 0xC4000 - 0xC7FFF - * 0x5B [1:0] 0xC8000 - 0xCBFFF - * 0x5B [5:4] 0xCC000 - 0xCFFFF - * 0x5C [1:0] 0xD0000 - 0xD3FFF - * 0x5C [5:4] 0xD4000 - 0xD7FFF - * 0x5D [1:0] 0xD8000 - 0xDBFFF - * 0x5D [5:4] 0xDC000 - 0xDFFFF - * 0x5E [1:0] 0xE0000 - 0xE3FFF - * 0x5E [5:4] 0xE4000 - 0xE7FFF - * 0x5F [1:0] 0xE8000 - 0xEBFFF - * 0x5F [5:4] 0xEC000 - 0xEFFFF - * 00 == DRAM Disabled (All Access go to memory mapped I/O space) - * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) - * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) - * 11 == Normal (All Access go to DRAM) - */ - - // Map all legacy ranges to DRAM - 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24), - 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24), - - /* DRB - DRAM Row Boundary Registers - * 0x60 - 0x6F - * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. - */ - // Conservatively say each row has 64MB of ram, we will fix this up later - // NOTE: These defaults allow us to prime all of the DIMMs on the board - // without jumping through 36-bit adddressing hoops, even if the - // total memory is > 4 GB. Changing these values may break do_ram_command()! - 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), - 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - - /* DRA - DRAM Row Attribute Register - * 0x70 Row 0,1 - * 0x71 Row 2,3 - * 0x72 Row 4,5 - * 0x73 Row 6,7 - * [7:7] Device width for Odd numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [6:4] Row Attributes for Odd numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (for dual-channel) - * Others == Reserved - * [3:3] Device width for Even numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [2:0] Row Attributes for Even numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (This page size appears broken) - * Others == Reserved - */ - // NOTE: overridden by configure_e7501_row_attributes(), later - 0x70, 0x00000000, 0, - - /* DRT - DRAM Timing Register - * 0x78 - * [31:30] Reserved - * [29:29] Back to Back Write-Read Turn Around - * 0 == 3 clocks between WR-RD commands - * 1 == 2 clocks between WR-RD commands - * [28:28] Back to Back Read-Write Turn Around - * 0 == 5 clocks between RD-WR commands - * 1 == 4 clocks between RD-WR commands - * [27:27] Back to Back Read Turn Around - * 0 == 4 clocks between RD commands - * 1 == 3 clocks between RD commands - * [26:24] Read Delay (tRD) - * 000 == 7 clocks - * 001 == 6 clocks - * 010 == 5 clocks - * Others == Reserved - * [23:19] Reserved - * [18:16] DRAM idle timer - * 000 == infinite - * 011 == 16 dram clocks - * 001 == 0 clocks - * [15:11] Reserved - * [10:09] Active to Precharge (tRAS) - * 00 == 7 clocks - * 01 == 6 clocks - * 10 == 5 clocks - * 11 == Reserved - * [08:06] Reserved - * [05:04] Cas Latency (tCL) - * 00 == 2.5 Clocks - * 01 == 2.0 Clocks - * 10 == Reserved (was 1.5 Clocks for E7500) - * 11 == Reserved - * [03:03] Write Ras# to Cas# Delay (tRCD) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - * [02:01] Read RAS# to CAS# Delay (tRCD) - * 00 == reserved - * 01 == reserved - * 10 == 3 DRAM Clocks - * 11 == 2 DRAM Clocks - * [00:00] DRAM RAS# to Precharge (tRP) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - */ - - // Some earlier settings: - /* Most aggressive settings possible */ -// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), -// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), -// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), - - // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and - // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. - 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), - - /* FIXME why was I attempting to set a reserved bit? */ - /* 0x0100040f */ - - /* DRC - DRAM Contoller Mode Register - * 0x7c - * [31:30] Reserved - * [29:29] Initialization Complete - * 0 == Not Complete - * 1 == Complete - * [28:23] Reserved - * [22:22] Channels - * 0 == Single channel - * 1 == Dual Channel - * [21:20] DRAM Data Integrity Mode - * 00 == Disabled, no ECC - * 01 == Reserved - * 10 == Error checking, using chip-kill, with correction - * 11 == Reserved - * [19:18] DRB Granularity (Read-Only) - * 00 == 32 MB quantities (single channel mode) - * 01 == 64 MB quantities (dual-channel mode) - * 10 == Reserved - * 11 == Reserved - * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) - * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) - * 0 == 2n Rule - * 1 == 1n rule - * [15:11] Reserved - * [10:08] Refresh mode select - * 000 == Refresh disabled - * 001 == Refresh interval 15.6 usec - * 010 == Refresh interval 7.8 usec - * 011 == Refresh interval 64 usec - * 111 == Refresh every 64 clocks (fast refresh) - * [07:07] Reserved - * [06:04] Mode Select (SMS) - * 000 == Reserved (was Self Refresh Mode in E7500) - * 001 == NOP Command - * 010 == All Banks Precharge - * 011 == Mode Register Set - * 100 == Extended Mode Register Set - * 101 == Reserved - * 110 == CBR Refresh - * 111 == Normal Operation - * [03:00] Reserved - */ -// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - - // Default to dual-channel mode, ECC, 1-clock address/cmd hold - // NOTE: configure_e7501_dram_controller_mode() configures further - 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), - - /* Another Intel undocumented register - * 0x88 - 0x8B - * [31:31] Purpose unknown - * [26:26] Master DLL Reset? - * 0 == Normal operation? - * 1 == Reset? - * [07:07] Periodic memory recalibration? - * 0 == Disabled? - * 1 == Enabled? - * [04:04] Receive FIFO RE-Sync? - * 0 == Normal operation? - * 1 == Reset? - */ - // NOTE: Some factory BIOSs don't do this. - // Doesn't seem to matter either way. - 0x88, 0xffffff00, 0x80, - - /* CLOCK_DIS - CK/CK# Disable Register - * 0x8C - * [7:7] DDR Frequency - * 0 == 100 MHz (200 MHz data rate) - * 1 == 133 MHz (266 MHz data rate) - * [6:4] Reserved - * [3:3] CK3 - * 0 == Enable - * 1 == Disable - * [2:2] CK2 - * 0 == Enable - * 1 == Disable - * [1:1] CK1 - * 0 == Enable - * 1 == Disable - * [0:0] CK0 - * 0 == Enable - * 1 == Disable - */ - // NOTE: Disable all clocks initially; turn ones we need back on - // in enable_e7501_clocks() - 0x8C, 0xfffffff0, 0xf, - - /* TOLM - Top of Low Memory Register - * 0xC4 - 0xC5 - * [15:11] Top of low memory (TOLM) - * The address below 4GB that should be treated as RAM, - * on a 128MB granularity. - * [10:00] Reserved - */ - /* REMAPBASE - Remap Base Address Regsiter - * 0xC6 - 0xC7 - * [15:10] Reserved - * [09:00] Remap Base Address [35:26] 64M aligned - * Bits [25:0] are assumed to be 0. - */ - - // NOTE: TOLM overridden by configure_e7501_ram_addresses() - 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16), - - /* REMAPLIMIT - Remap Limit Address Register - * 0xC8 - 0xC9 - * [15:10] Reserved - * [09:00] Remap Limit Address [35:26] 64M aligned - * When remaplimit < remapbase the remap window is disabled. - */ - 0xc8, 0xfffffc00, 0, - - /* DVNP - Device Not Present Register - * 0xE0 - 0xE1 - * [15:05] Reserved - * [04:04] Device 4 Function 1 Present - * 0 == Present - * 1 == Absent - * [03:03] Device 3 Function 1 Present - * 0 == Present - * 1 == Absent - * [02:02] Device 2 Function 1 Present - * 0 == Present - * 1 == Absent - * [01:01] Reserved - * [00:00] Device 0 Function 1 Present - * 0 == Present - * 1 == Absent - */ - - // Enable D0:D1, disable D2:F1, D3:F1, D4:F1 - 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), - - // Undocumented - 0xd8, 0xffff9fff, 0x00000000, - - // Undocumented - this is pure conjecture based on similarity to 855PM - /* MCHTST - MCH Test Register - * 0xF4 - 0xF7 - * [31:31] Purpose unknown - * [30:30] Purpose unknown - * [29:23] Unknown - not used? - * [22:22] System Memory MMR Enable - * 0 == Disable: mem space and BAR at 0x14 are not accessible - * 1 == Enable: mem space and BAR at 0x14 are accessible - * [21:20] Purpose unknown - * [19:02] Unknown - not used? - * [01:01] D6EN (Device #6 enable) - * 0 == Disable - * 1 == Enable - * [00:00] Unknown - not used? - */ - - 0xf4, 0x3f8ffffd, 0x40300002, - -#ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. - // This will access D2:F0:0x50, is this correct?? - 0x1050, 0xffffffcf, 0x00000030, -#endif -}; - - /* DDR RECOMP tables */ - -// Slew table for 1x drive? -static const uint32_t maybe_1x_slew_table[] = { - 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, - 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, -}; - -// Slew table for 2x drive? -static const uint32_t maybe_2x_slew_table[] = { - 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, - 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, -}; - -// Pull Up / Pull Down offset table, if analogous to IXP2800? -static const uint32_t maybe_pull_updown_offset_table[] = { - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x88888888, 0x88888888, 0x88888888, 0x88888888, -}; - -/*----------------------------------------------------------------------------- -Delay functions: ------------------------------------------------------------------------------*/ - -#define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) -{ - int i; - for (i = 0; i < 16; i++) { - SLOW_DOWN_IO; - } -} - -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif - -#define EXTRA_DELAY DO_DELAY - -static void die_on_spd_error(int spd_return_value) -{ - if (spd_return_value < 0) - die("Error reading SPD info\n"); -} - -/*----------------------------------------------------------------------------- -Serial presence detect (SPD) functions: ------------------------------------------------------------------------------*/ - -/** - * Calculate the page size for each physical bank of the DIMM: - * log2(page size) = (# columns) + log2(data width) - * - * NOTE: Page size is the total number of data bits in a row. - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return log2(page size) for each side of the DIMM. - */ -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) -{ - uint16_t module_data_width; - int value; - struct dimm_size pgsz; - - pgsz.side1 = 0; - pgsz.side2 = 0; - - // Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) - goto hw_err; - pgsz.side1 = value & 0xf; // # columns in bank 1 - - /* Get the module data width and convert it to a power of two */ - value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); - if (value < 0) - goto hw_err; - module_data_width = (value & 0xff) << 8; - - value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); - if (value < 0) - goto hw_err; - module_data_width |= (value & 0xff); - - pgsz.side1 += log2(module_data_width); - - /* side two */ - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - if (value < 0) - goto hw_err; - if (value > 2) - die("Bad SPD value\n"); - if (value == 2) { - - pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently - value = - spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) - goto hw_err; - if ((value & 0xf0) != 0) { - // Asymmetric banks - pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ - pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ - } - } - - return pgsz; - - hw_err: - die(SPD_ERROR); - return pgsz; // Never reached -} - -/** - * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return Width in bits of each DIMM side's DRAMs. - */ -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) -{ - int value; - struct dimm_size width; - - width.side1 = 0; - width.side2 = 0; - - value = - spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); - die_on_spd_error(value); - - width.side1 = value & 0x7f; // Mask off bank 2 flag - - if (value & 0x80) { - width.side2 = width.side1 << 1; // Bank 2 exists and is double-width - } else { - // If bank 2 exists, it's the same width as bank 1 - value = - spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - die_on_spd_error(value); - -#ifdef ROMCC_IF_BUG_FIXED - if (value == 2) - width.side2 = width.side1; -#else - switch (value) { - case 2: - width.side2 = width.side1; - break; - - default: - break; - } -#endif - } - - return width; -} - -/** - * Calculate the log base 2 size in bits of both DIMM sides. - * - * log2(# bits) = (# columns) + log2(data width) + - * (# rows) + log2(banks per SDRAM) - * - * Note that it might be easier to use SPD byte 31 here, it has the DIMM size - * as a multiple of 4MB. The way we do it now we can size both sides of an - * asymmetric DIMM. - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return log2(number of bits) for each side of the DIMM. - */ -static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) -{ - int value; - - // Start with log2(page size) - struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); - - if (sz.side1 > 0) { - - value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); - die_on_spd_error(value); - - sz.side1 += value & 0xf; - - if (sz.side2 > 0) { - - // Double-sided DIMM - if (value & 0xF0) - sz.side2 += value >> 4; // Asymmetric - else - sz.side2 += value; // Symmetric - } - - value = - spd_read_byte(dimm_socket_address, - SPD_NUM_BANKS_PER_SDRAM); - die_on_spd_error(value); - - value = log2(value); - sz.side1 += value; - if (sz.side2 > 0) - sz.side2 += value; - } - - return sz; -} - -#ifdef VALIDATE_DIMM_COMPATIBILITY - -/** - * Determine whether two DIMMs have the same value for an SPD parameter. - * - * @param spd_byte_number The SPD byte number to compare in both DIMMs. - * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. - * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. - * @return 1 if both DIMM sockets report the same value for the specified - * SPD parameter, 0 if the values differed or an error occurred. - */ -static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) -{ - uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); - int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); - - if ((dimm0_value >= 0) && (dimm1_value >= 0) - && (dimm0_value == dimm1_value)) - bEqual = 1; - - return bEqual; -} -#endif - -/** - * Scan for compatible DIMMs. - * - * The code in this module only supports dual-channel operation, so we test - * that compatible DIMMs are paired. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @return A bitmask indicating which of the possible sockets for each channel - * was found to contain a compatible DIMM. - * Bit 0 corresponds to the closest socket for channel 0 - * Bit 1 to the next socket for channel 0 - * ... - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 - * ... - * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 - */ -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) -{ - int i; - uint8_t dimm_mask = 0; - - // Have to increase size of dimm_mask if this assertion is violated - ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); - - // Find DIMMs we can support on channel 0. - // Then see if the corresponding channel 1 DIMM has the same parameters, - // since we only support dual-channel. - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t channel0_dimm = ctrl->channel0[i]; - uint16_t channel1_dimm = ctrl->channel1[i]; - uint8_t bDualChannel = 1; -#ifdef VALIDATE_DIMM_COMPATIBILITY - struct dimm_size page_size; - struct dimm_size sdram_width; -#endif - int spd_value; - - if (channel0_dimm == 0) - continue; // No such socket on this mainboard - - if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != - SPD_MEMORY_TYPE_SDRAM_DDR) - continue; - -#ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != - SPD_VOLTAGE_SSTL2) - continue; // Unsupported voltage - - // E7501 does not support unregistered DIMMs - spd_value = - spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); - if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) - continue; - - // Must support burst = 4 for dual-channel operation on E7501 - // NOTE: for single-channel, burst = 8 is required - spd_value = - spd_read_byte(channel0_dimm, - SPD_SUPPORTED_BURST_LENGTHS); - if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) - continue; - - page_size = sdram_spd_get_page_size(channel0_dimm); - sdram_width = sdram_spd_get_width(channel0_dimm); - - // Validate DIMM page size - // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel - // NOTE: 4 KB = 32 Kb = 2^15 - // 32 KB = 262 Kb = 2^18 - - if ((page_size.side1 < 15) || (page_size.side1 > 18)) - continue; - - // If DIMM is double-sided, verify side2 page size - if (page_size.side2 != 0) { - if ((page_size.side2 < 15) - || (page_size.side2 > 18)) - continue; - } - // Validate SDRAM width - // The E7501 only supports x4 and x8 devices - - if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8)) - continue; - - // If DIMM is double-sided, verify side2 width - if (sdram_width.side2 != 0) { - if ((sdram_width.side2 != 4) - && (sdram_width.side2 != 8)) - continue; - } -#endif - // Channel 0 DIMM looks compatible. - // Now see if it is paired with the proper DIMM on channel 1. - - ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? - - // NOTE: unpopulated DIMMs cause read to fail - spd_value = - spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); - if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { - - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); - continue; - } -#ifdef VALIDATE_DIMM_COMPATIBILITY - spd_value = - spd_read_byte(channel1_dimm, - SPD_SUPPORTED_BURST_LENGTHS); - if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) - continue; - - int j; - for (j = 0; j < sizeof(dual_channel_parameters); ++j) { - if (!are_spd_values_equal - (dual_channel_parameters[j], channel0_dimm, - channel1_dimm)) { - - bDualChannel = 0; - break; - } - } -#endif - - // Code around ROMCC bug in optimization of "if" statements -#ifdef ROMCC_IF_BUG_FIXED - if (bDualChannel) { - // Made it through all the checks, this DIMM pair is usable - dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i))); - } else - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); -#else - switch (bDualChannel) { - case 0: - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); - break; - - default: - // Made it through all the checks, this DIMM pair is usable - dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)); - break; - } -#endif - } - - return dimm_mask; -} - -/*----------------------------------------------------------------------------- -SDRAM configuration functions: ------------------------------------------------------------------------------*/ - -/** - * Send the specified command to all DIMMs. - * - * @param command Specifies the command to be sent to the DIMMs. - * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. - */ -static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) -{ - int i; - uint32_t dram_controller_mode; - uint8_t dimm_start_64M_multiple = 0; - uint16_t e7501_mode_bits = jedec_mode_bits; - - // Configure the RAM command - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode &= 0xFFFFFF8F; - dram_controller_mode |= command; - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - - // RAM_COMMAND_NORMAL is an exception. - // It affects only the memory controller and does not need to be "sent" to the DIMMs. - - if (command != RAM_COMMAND_NORMAL) { - - // Send the command to all DIMMs by accessing a memory location within each - // NOTE: for mode select commands, some of the location address bits - // are part of the command - - // Map JEDEC mode bits to E7501 - if (command == RAM_COMMAND_MRS) { - // Host address lines [15:5] map to DIMM address lines [12:11, 9:1] - // The E7501 hard-sets DIMM address lines 10 & 0 to zero - - ASSERT(!(jedec_mode_bits & 0x0401)); - - e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15 - ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13 - - } else if (command == RAM_COMMAND_EMRS) { - // Host address lines [15:3] map to DIMM address lines [12:0] - e7501_mode_bits = jedec_mode_bits <<= 3; - } else - ASSERT(jedec_mode_bits == 0); - - dimm_start_64M_multiple = 0; - - for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - - uint8_t dimm_end_64M_multiple = - pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); - if (dimm_end_64M_multiple > dimm_start_64M_multiple) { - - // This code assumes DRAM row boundaries are all set below 4 GB - // NOTE: 0x40 * 64 MB == 4 GB - ASSERT(dimm_start_64M_multiple < 0x40); - - // NOTE: 2^26 == 64 MB - - uint32_t dimm_start_address = - dimm_start_64M_multiple << 26; - - RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); - RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); - RAM_DEBUG_MESSAGE("\n"); - - read32(dimm_start_address + e7501_mode_bits); - - // Set the start of the next DIMM - dimm_start_64M_multiple = - dimm_end_64M_multiple; - } - } - } -} - -/** - * Set the mode register of all DIMMs. - * - * The proper CAS# latency setting is added to the mode bits specified - * by the caller. - * - * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. - */ -static void set_ram_mode(uint16_t jedec_mode_bits) -{ - ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); - - uint32_t dram_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; - - switch (dram_cas_latency) { - case DRT_CAS_2_5: - jedec_mode_bits |= SDRAM_CAS_2_5; - break; - - case DRT_CAS_2_0: - jedec_mode_bits |= SDRAM_CAS_2_0; - break; - - default: - BUG(); - break; - } - - do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); -} - -/*----------------------------------------------------------------------------- -DIMM-independant configuration functions: ------------------------------------------------------------------------------*/ - -/** - * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory - * present in the specified DIMM. - * - * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of - * the DIMM. - * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of - * 64 MB) for DIMMs < dimm_index. - * @param dimm_index Which DIMM pair is being processed - * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). - * @return New multiple of 64 MB total DRAM in the system. - */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) -{ - int i; - - ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL); - - // DIMM sides must be at least 32 MB - ASSERT(dimm_log2_num_bits.side1 >= 28); - ASSERT((dimm_log2_num_bits.side2 == 0) - || (dimm_log2_num_bits.side2 >= 28)); - - // In dual-channel mode, we are called only once for each pair of DIMMs. - // Each time we process twice the capacity of a single DIMM. - - // Convert single DIMM capacity to paired DIMM capacity - // (multiply by two ==> add 1 to log2) - dimm_log2_num_bits.side1++; - if (dimm_log2_num_bits.side2 > 0) - dimm_log2_num_bits.side2++; - - // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) - // to the total capacity of the system - // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 - - total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); - - // Configure the boundary address for the row on side 1 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), - total_dram_64M_multiple); - - // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair - // (as a multiple of 64 MB) to the total capacity of the system - if (dimm_log2_num_bits.side2 >= 29) - total_dram_64M_multiple += - (1 << (dimm_log2_num_bits.side2 - 29)); - - // Configure the boundary address for the row (if any) on side 2 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1), - total_dram_64M_multiple); - - // Update boundaries for rows subsequent to these. - // These settings will be overridden by a subsequent call if a populated physical slot exists - - for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1), - total_dram_64M_multiple); - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1), - total_dram_64M_multiple); - } - - return total_dram_64M_multiple; -} - -/** - * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). - * - * If necessary, set up a remap window so we don't waste DRAM that ordinarily - * would lie behind addresses reserved for memory-mapped I/O. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void configure_e7501_ram_addresses(const struct mem_controller - *ctrl, uint8_t dimm_mask) -{ - int i; - uint8_t total_dram_64M_multiple = 0; - - // Configure the E7501's DRAM row boundaries - // Start by zeroing out the temporary initial configuration - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t dimm_socket_address = ctrl->channel0[i]; - struct dimm_size sz; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present - - sz = spd_get_dimm_size(dimm_socket_address); - - RAM_DEBUG_MESSAGE("dimm size ="); - RAM_DEBUG_HEX32((u32)sz.side1); - RAM_DEBUG_MESSAGE(" "); - RAM_DEBUG_HEX32((u32)sz.side2); - RAM_DEBUG_MESSAGE("\n"); - - if (sz.side1 == 0) - die("Bad SPD value\n"); - - total_dram_64M_multiple = - configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); - } - - // Configure the Top Of Low Memory (TOLM) in the E7501 - // This address must be a multiple of 128 MB that is less than 4 GB. - // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address - // in the highest 5 bits. - - // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. - // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes - // such as flash and memory-mapped I/O. - - // If there is more than 3 GB of DRAM, we define a remap window which - // makes the DRAM "behind" the reserved region available above the top of physical - // memory. - - // NOTE: 0xC0000000 / (64 MB) == 0x30 - - if (total_dram_64M_multiple <= 0x30) { - - // <= 3 GB total RAM - - /* I should really adjust all of this in C after I have resources - * to all of the pci devices. - */ - - // Round up to 128MB granularity - // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down? - - uint8_t total_dram_128M_multiple = - (total_dram_64M_multiple + 1) >> 1; - - // Convert to high 16 bits of address - uint16_t top_of_low_memory = - total_dram_128M_multiple << 11; - - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, - top_of_low_memory); - - } else { - - // > 3 GB total RAM - - // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory - uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 - uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF - - // Put TOLM at 3 GB - - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000); - - // Define a remap window to make the RAM that would appear from 3 GB - 4 GB - // visible just beyond 4 GB or the end of physical memory, whichever is larger - // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, - // (i.e. a multiple of 64 MB) in the lowest 10 bits. - // NOTE: 0x100000000 / (64 MB) == 0x40 - - if (total_dram_64M_multiple < 0x40) { - remap_base = 0x40; // 0x100000000 - remap_limit = - 0x40 + (total_dram_64M_multiple - 0x30) - 1; - } - - pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, - remap_base); - pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, - remap_limit); - } -} - -/** - * If we're configured to use ECC, initialize the SDRAM and clear the E7501's - * ECC error flags. - */ -static void initialize_ecc(void) -{ - uint32_t dram_controller_mode; - - /* Test to see if ECC support is enabled */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode >>= 20; - dram_controller_mode &= 3; - if (dram_controller_mode == 2) { - - uint8_t byte; - - RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); - /* Initialize ECC bits , use ECC zero mode (new to 7501) */ - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); - - // Wait for scrub cycle to complete - do { - byte = - pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); - } while ((byte & 0x08) == 0); - - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); - RAM_DEBUG_MESSAGE("ECC state initialized.\n"); - - /* Clear the ECC error bits */ - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); - - // Clear DRAM Interface error bits (write-one-clear) - pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); - pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); - - // Start normal ECC scrub - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); - } - -} - -/** - * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# - * latency, which is assumed to have been programmed already), based on the - * parameters of the various installed DIMMs. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void configure_e7501_dram_timing(const struct mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - uint32_t dram_timing; - int value; - uint8_t slowest_row_precharge = 0; - uint8_t slowest_ras_cas_delay = 0; - uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; - - // CAS# latency must be programmed beforehand - ASSERT((current_cas_latency == DRT_CAS_2_0) - || (current_cas_latency == DRT_CAS_2_5)); - - // Each timing parameter is determined by the slowest DIMM - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_ROW_PRECHARGE_TIME); - if (value < 0) - goto hw_err; - if (value > slowest_row_precharge) - slowest_row_precharge = value; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_RAS_TO_CAS_DELAY); - if (value < 0) - goto hw_err; - if (value > slowest_ras_cas_delay) - slowest_ras_cas_delay = value; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (value < 0) - goto hw_err; - if (value > slowest_active_to_precharge_delay) - slowest_active_to_precharge_delay = value; - } - - // NOTE for timing parameters: - // At 133 MHz, 1 clock == 7.52 ns - - /* Read the initial state */ - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); - - /* Trp */ - - // E7501 supports only 2 or 3 clocks for tRP - if (slowest_row_precharge > ((22 << 2) | (2 << 0))) - die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks - else if (slowest_row_precharge > (15 << 2)) - dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks - else - dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks - - /* Trcd */ - - // E7501 supports only 2 or 3 clocks for tRCD - // Use the same value for both read & write - dram_timing &= ~((1 << 3) | (3 << 1)); - if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) - die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks - else if (slowest_ras_cas_delay > (15 << 2)) - dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks - else - dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks - - /* Tras */ - - // E7501 supports only 5, 6, or 7 clocks for tRAS - // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns - dram_timing &= ~(3 << 9); - - if (slowest_active_to_precharge_delay > 52) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks - else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0 << 9); // 46-52 ns: 7 clocks - else if (slowest_active_to_precharge_delay > 37) - dram_timing |= (1 << 9); // 38-45 ns: 6 clocks - else - dram_timing |= (2 << 9); // < 38 ns: 5 clocks - - /* Trd */ - - /* Set to a 7 clock read delay. This is for 133MHz - * with a CAS latency of 2.5 if 2.0 a 6 clock - * delay is good */ - - dram_timing &= ~(7 << 24); // 7 clocks - if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1 << 24); // 6 clocks - - /* - * Back to Back Read-Write Turn Around - */ - /* Set to a 5 clock back to back read to write turn around. - * 4 is a good delay if the CAS latency is 2.0 */ - - dram_timing &= ~(1 << 28); // 5 clocks - if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1 << 28); // 4 clocks - - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); - - return; - - hw_err: - die(SPD_ERROR); -} - -/** - * Determine the shortest CAS# latency that the E7501 and all DIMMs have in - * common, and program the E7501 to use it. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_cas_latency(const struct mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - int value; - uint32_t dram_timing; - uint16_t maybe_dram_read_timing; - uint32_t dword; - - // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format - // NOTE: E7501 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = - SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; - uint32_t current_cas_latency; - uint32_t dimm_compatible_cas_latencies; - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - value = - spd_read_byte(dimm_socket_address, - SPD_ACCEPTABLE_CAS_LATENCIES); - if (value < 0) - goto hw_err; - - dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM - current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM - - // Can we support the highest CAS# latency? - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (value < 0) - goto hw_err; - - // NOTE: At 133 MHz, 1 clock == 7.52 ns - if (value > 0x75) { - // Our bus is too fast for this CAS# latency - // Remove it from the bitmask of those supported by the DIMM that are compatible - dimm_compatible_cas_latencies &= ~current_cas_latency; - } - // Can we support the next-highest CAS# latency (max - 0.5)? - - current_cas_latency >>= 1; - if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, - SPD_SDRAM_CYCLE_TIME_2ND); - if (value < 0) - goto hw_err; - if (value > 0x75) - dimm_compatible_cas_latencies &= - ~current_cas_latency; - } - // Can we support the next-highest CAS# latency (max - 1.0)? - current_cas_latency >>= 1; - if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, - SPD_SDRAM_CYCLE_TIME_3RD); - if (value < 0) - goto hw_err; - if (value > 0x75) - dimm_compatible_cas_latencies &= - ~current_cas_latency; - } - // Restrict the system to CAS# latencies compatible with this DIMM - system_compatible_cas_latencies &= - dimm_compatible_cas_latencies; - - /* go to the next DIMM */ - } - - /* After all of the arduous calculation setup with the fastest - * cas latency I can use. - */ - - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); - dram_timing &= ~(DRT_CAS_MASK); - - maybe_dram_read_timing = - pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); - maybe_dram_read_timing &= 0xF00C; - - if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { - dram_timing |= DRT_CAS_2_0; - maybe_dram_read_timing |= 0xBB1; - } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { - - uint32_t dram_row_attributes = - pci_read_config32(PCI_DEV(0, 0, 0), DRA); - - dram_timing |= DRT_CAS_2_5; - - // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly - // different value if all DIMM slots are populated - - if ((dram_row_attributes & 0xff) - && (dram_row_attributes & 0xff00) - && (dram_row_attributes & 0xff0000) - && (dram_row_attributes & 0xff000000)) { - - // All slots populated - maybe_dram_read_timing |= 0x0882; - } else { - // Some unpopulated slots - maybe_dram_read_timing |= 0x0662; - } - } else - die("No CAS# latencies compatible with all DIMMs!!\n"); - - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); - - /* set master DLL reset */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); - dword |= (1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ - dword |= 0xd2109800; - - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, - maybe_dram_read_timing); - - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ - dword &= ~(1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - return; - - hw_err: - die(SPD_ERROR); -} - -/** - * Configure the refresh interval so that we refresh no more often than - * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs - * don't support it. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_dram_controller_mode(const struct - mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - - // Initial settings - uint32_t controller_mode = - pci_read_config32(PCI_DEV(0, 0, 0), DRC); - uint32_t system_refresh_mode = (controller_mode >> 8) & 7; - - // Code below assumes that most aggressive settings are in - // force when we are called, either via E7501 reset defaults - // or by sdram_set_registers(): - // - ECC enabled - // - No refresh - - ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC - ASSERT(!(controller_mode & (7 << 8))); // Refresh - - /* Walk through _all_ dimms and find the least-common denominator for: - * - ECC support - * - refresh rates - */ - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - - uint32_t dimm_refresh_mode; - int value; - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) { - continue; // This DIMM not usable - } - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - // Disable ECC mode if any one of the DIMMs does not support ECC - // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. - - value = - spd_read_byte(dimm_socket_address, - SPD_DIMM_CONFIG_TYPE); - die_on_spd_error(value); - if (value != ERROR_SCHEME_ECC) { - controller_mode &= ~(3 << 20); - } - - value = spd_read_byte(dimm_socket_address, SPD_REFRESH); - die_on_spd_error(value); - value &= 0x7f; // Mask off self-refresh bit - if (value > MAX_SPD_REFRESH_RATE) { - print_err("unsupported refresh rate\n"); - continue; - } - // Get the appropriate E7501 refresh mode for this DIMM - dimm_refresh_mode = refresh_rate_map[value]; - if (dimm_refresh_mode > 7) { - print_err("unsupported refresh rate\n"); - continue; - } - // If this DIMM requires more frequent refresh than others, - // update the system setting - if (refresh_frequency[dimm_refresh_mode] > - refresh_frequency[system_refresh_mode]) - system_refresh_mode = dimm_refresh_mode; - -#ifdef SUSPICIOUS_LOOKING_CODE -// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. - - // Switch to 2 clocks for address/command if required by any one of the DIMMs - // NOTE: At 133 MHz, 1 clock == 7.52 ns - value = - spd_read_byte(dimm_socket_address, - SPD_CMD_SIGNAL_INPUT_HOLD_TIME); - die_on_spd_error(value); - if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ - controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */ - } -#endif - - /* go to the next DIMM */ - } - - controller_mode |= (system_refresh_mode << 8); - - // Configure the E7501 - pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); -} - -/** - * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM - * parameters read via SPD. This tells the controller the width of the SDRAM - * chips on each DIMM side (x4 or x8) and the page size of each DIMM side - * (4, 8, 16, or 32 KB). - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) -{ - int i; - uint32_t row_attributes = 0; - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t dimm_socket_address = ctrl->channel0[i]; - struct dimm_size page_size; - struct dimm_size sdram_width; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable - - // Get the relevant parameters via SPD - page_size = sdram_spd_get_page_size(dimm_socket_address); - sdram_width = sdram_spd_get_width(dimm_socket_address); - - // Update the DRAM Row Attributes. - // Page size is encoded as log2(page size in bits) - log2(8 Kb) - // NOTE: 8 Kb = 2^13 - row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row - - if (sdram_width.side2 > 0) - row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD - - // Set x4 flags if appropriate - if (sdram_width.side1 == 4) { - row_attributes |= 0x08 << (i << 3); - } - - if (sdram_width.side2 == 4) { - row_attributes |= 0x08 << ((i << 3) + 4); - } - - /* go to the next DIMM */ - } - - /* Write the new row attributes register */ - pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); -} - -/* - * Enable clock signals for populated DIMM sockets and disable them for - * unpopulated sockets (to reduce EMI). - * - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void enable_e7501_clocks(uint8_t dimm_mask) -{ - int i; - uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint8_t socket_mask = 1 << i; - - if (dimm_mask & socket_mask) - clock_disable &= ~socket_mask; // DIMM present, enable clock - else - clock_disable |= socket_mask; // DIMM absent, disable clock - } - - pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); -} - -/* DIMM-dedependent configuration functions */ - -/** - * DDR Receive FIFO RE-Sync (?) - */ -static void RAM_RESET_DDR_PTR(void) -{ - uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); - byte |= (1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); - - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); - byte &= ~(1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); -} - -/** - * Set E7501 registers that are either independent of DIMM specifics, or - * establish default settings that will be overridden when we learn the - * specifics. - * - * This sets PCI configuration registers to known good values based on the - * table 'constant_register_values', which are a triple of configuration - * register offset, mask, and bits to set. - */ -static void ram_set_d0f0_regs(void) -{ - int i; - int num_values = ARRAY_SIZE(constant_register_values); - - ASSERT((num_values % 3) == 0); // Bad table? - - for (i = 0; i < num_values; i += 3) { - - uint32_t register_offset = constant_register_values[i]; - uint32_t bits_to_mask = constant_register_values[i + 1]; - uint32_t bits_to_set = constant_register_values[i + 2]; - uint32_t register_value; - - // It's theoretically possible to set values for something other than D0:F0, - // but it's not typically done here - ASSERT(!(register_offset & 0xFFFFFF00)); - - // bits_to_mask and bits_to_set should not reference the same bits - // Again, not strictly an error, but flagged as a potential bug - ASSERT((bits_to_mask & bits_to_set) == 0); - - register_value = - pci_read_config32(PCI_DEV(0, 0, 0), register_offset); - register_value &= bits_to_mask; - register_value |= bits_to_set; - - pci_write_config32(PCI_DEV(0, 0, 0), register_offset, - register_value); - } -} - -/** - * Copy 64 bytes from one location to another. - * - * @param src_addr TODO - * @param dst_addr TODO - */ -static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) -{ - int i; - for (i = 0; i < 8; i++) { - write32(dst_addr, *src_addr); - src_addr++; - dst_addr += sizeof(uint32_t); - } -} - -/** - * Set the E7501's (undocumented) RCOMP registers. - * - * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, - * RCOMP registers appear to affect drive strength, pullup/pulldown offset, - * and slew rate of various signal groups. - * - * Comments below are conjecture based on apparent similarity between the - * E7501 and these two chips. - */ -static void ram_set_rcomp_regs(void) -{ - uint32_t dword; - uint8_t maybe_strength_control; - - RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); - - /*enable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword |= (1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); - - // Set the RCOMP MMIO base address - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); - - // Block RCOMP updates while we configure the registers - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword |= (1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Begin to write the RCOMP registers */ - - // Set CMD and DQ/DQS strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; - maybe_strength_control |= 0x44; - write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); - write16(RCOMP_MMIO + 0x42, 0); - - write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60); - - // NOTE: some factory BIOS set 0x9088 here. Seems to work either way. - write16(RCOMP_MMIO + 0x40, 0); - - // Set RCVEnOut# strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); - write16(RCOMP_MMIO + 0x50, 0); - - // Set CS# strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); - write16(RCOMP_MMIO + 0x48, 0); - - // Set CKE strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); - write16(RCOMP_MMIO + 0x44, 0); - - // Set CK strength for x4 SDRAM to 1x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8; - maybe_strength_control |= 1; - write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); - - write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); - write16(RCOMP_MMIO + 0x4c, 0); - - write8(RCOMP_MMIO + 0x2c, 0xff); - - // Set the digital filter length to 8 (?) - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - - // NOTE: Some factory BIOS don't do this. - // Doesn't seem to matter either way. - dword &= ~2; - - dword |= 1; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Wait 40 usec */ - SLOW_DOWN_IO; - - /* unblock updates */ - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword &= ~(1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - // Force a RCOMP measurement cycle? - dword |= (1 << 8); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - dword &= ~(1 << 8); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Wait 40 usec */ - SLOW_DOWN_IO; - - /*disable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword &= ~(1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); - -} - -/*----------------------------------------------------------------------------- -Public interface: ------------------------------------------------------------------------------*/ - -/** - * Go through the JEDEC initialization sequence for all DIMMs, then enable - * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up - * and running. - * - * @param controllers Not used. - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) -{ - uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); - uint32_t dram_controller_mode; - - if (dimm_mask == 0) - return; - - /* 1 & 2 Power up and start clocks */ - RAM_DEBUG_MESSAGE("Ram Enable 1\n"); - RAM_DEBUG_MESSAGE("Ram Enable 2\n"); - - /* A 200us delay is needed */ - DO_DELAY; EXTRA_DELAY; - - /* 3. Apply NOP */ - RAM_DEBUG_MESSAGE("Ram Enable 3\n"); - do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; - - /* 4 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 4\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; - /* wait until the all banks idle state... */ - - /* 5. Issue EMRS to enable DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 5\n"); - do_ram_command(RAM_COMMAND_EMRS, - SDRAM_EXTMODE_DLL_ENABLE | - SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; - - /* 6. Reset DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 6\n"); - set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); - EXTRA_DELAY; - /* Ensure a 200us delay between the DLL reset in step 6 and the final - * mode register set in step 9. - * Infineon needs this before any other command is sent to the ram. - */ - DO_DELAY; EXTRA_DELAY; - - /* 7 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 7\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; - - /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - - /* 9 mode register set */ - RAM_DEBUG_MESSAGE("Ram Enable 9\n"); - set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; - - /* 10 DDR Receive FIFO RE-Sync */ - RAM_DEBUG_MESSAGE("Ram Enable 10\n"); - RAM_RESET_DDR_PTR(); - EXTRA_DELAY; - - /* 11 normal operation */ - RAM_DEBUG_MESSAGE("Ram Enable 11\n"); - do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; - - // Reconfigure the row boundaries and Top of Low Memory - // to match the true size of the DIMMs - configure_e7501_ram_addresses(ctrl, dimm_mask); - - /* Finally enable refresh */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode |= (1 << 29); - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - EXTRA_DELAY; - initialize_ecc(); - - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ - dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); - DUMPNORTH(); -} - -/** - * Configure SDRAM controller parameters that depend on characteristics of the - * DIMMs installed in the system. These characteristics are read from the - * DIMMs via the standard Serial Presence Detect (SPD) interface. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - uint8_t dimm_mask; - - RAM_DEBUG_MESSAGE("Reading SPD data...\n"); - - dimm_mask = spd_get_supported_dimms(ctrl); - - if (dimm_mask == 0) { - print_debug("No usable memory for this controller\n"); - } else { - enable_e7501_clocks(dimm_mask); - - RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); - - configure_e7501_row_attributes(ctrl, dimm_mask); - configure_e7501_dram_controller_mode(ctrl, dimm_mask); - configure_e7501_cas_latency(ctrl, dimm_mask); - RAM_RESET_DDR_PTR(); - - configure_e7501_dram_timing(ctrl, dimm_mask); - DO_DELAY; - RAM_DEBUG_MESSAGE("done\n"); - } - - /* NOTE: configure_e7501_ram_addresses() is NOT called here. - * We want to keep the default 64 MB/row mapping until sdram_enable() is called, - * even though the default mapping is almost certainly incorrect. - * The default mapping makes it easy to initialize all of the DIMMs - * even if the total system memory is > 4 GB. - * - * Save the dimm_mask for when sdram_enable is called, so it can call - * configure_e7501_ram_addresses() without having to regenerate the bitmask - * of usable DIMMs. - */ - pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); -} - -/** - * Do basic RAM setup that does NOT depend on serial presence detect - * information (i.e. independent of DIMM specifics). - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); - DUMPNORTH(); - - ram_set_rcomp_regs(); - ram_set_d0f0_regs(); -} diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h deleted file mode 100644 index 05c3889..0000000 --- a/src/northbridge/intel/e7501/raminit.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef RAMINIT_H -#define RAMINIT_H - -#define MAX_DIMM_SOCKETS_PER_CHANNEL 4 -#define MAX_NUM_CHANNELS 2 -#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) - -struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller - - // SMBus addresses of DIMM slots for each channel, - // in order from closest to MCH to furthest away - // 0 == not present - uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; - uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); - -#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7501/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig index 426ac0b..26c1476 100644 --- a/src/southbridge/intel/Kconfig +++ b/src/southbridge/intel/Kconfig @@ -6,7 +6,6 @@ source src/southbridge/intel/i82801ax/Kconfig source src/southbridge/intel/i82801bx/Kconfig source src/southbridge/intel/i82801cx/Kconfig source src/southbridge/intel/i82801dx/Kconfig -source src/southbridge/intel/i82801ex/Kconfig source src/southbridge/intel/i82801gx/Kconfig source src/southbridge/intel/i82801ix/Kconfig source src/southbridge/intel/i82870/Kconfig diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc index dd20d46..76ea2a4 100644 --- a/src/southbridge/intel/Makefile.inc +++ b/src/southbridge/intel/Makefile.inc @@ -6,7 +6,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig deleted file mode 100644 index caa5c79..0000000 --- a/src/southbridge/intel/i82801ex/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -config SOUTHBRIDGE_INTEL_I82801EX - bool - select SOUTHBRIDGE_INTEL_COMMON - select IOAPIC - select HAVE_HARD_RESET - select HAVE_USBDEBUG - -if SOUTHBRIDGE_INTEL_I82801EX - -config EHCI_BAR - hex - default 0xfef00000 - -endif diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc deleted file mode 100644 index fb76a98..0000000 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -ramstage-y += i82801ex.c -ramstage-y += uhci.c -ramstage-y += lpc.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += ehci.c -ramstage-y += smbus.c -ramstage-y += pci.c -ramstage-y += ac97.c -ramstage-y += watchdog.c -ramstage-y += reset.c diff --git a/src/southbridge/intel/i82801ex/ac97.c b/src/southbridge/intel/i82801ex/ac97.c deleted file mode 100644 index 08efe15..0000000 --- a/src/southbridge/intel/i82801ex/ac97.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = ac97_set_subsystem, -}; -static struct device_operations ac97_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97_audio_driver __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO, -}; -static const struct pci_driver ac97_modem_driver __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM, -}; diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h deleted file mode 100644 index 291fcd7..0000000 --- a/src/southbridge/intel/i82801ex/chip.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef I82801EX_CHIP_H -#define I82801EX_CHIP_H - -struct southbridge_intel_i82801ex_config -{ - -#define ICH5R_GPIO_USE_MASK 0x03 -#define ICH5R_GPIO_USE_DEFAULT 0x00 -#define ICH5R_GPIO_USE_AS_NATIVE 0x01 -#define ICH5R_GPIO_USE_AS_GPIO 0x02 - -#define ICH5R_GPIO_SEL_MASK 0x0c -#define ICH5R_GPIO_SEL_DEFAULT 0x00 -#define ICH5R_GPIO_SEL_OUTPUT 0x04 -#define ICH5R_GPIO_SEL_INPUT 0x08 - -#define ICH5R_GPIO_LVL_MASK 0x30 -#define ICH5R_GPIO_LVL_DEFAULT 0x00 -#define ICH5R_GPIO_LVL_LOW 0x10 -#define ICH5R_GPIO_LVL_HIGH 0x20 -#define ICH5R_GPIO_LVL_BLINK 0x30 - -#define ICH5R_GPIO_INV_MASK 0xc0 -#define ICH5R_GPIO_INV_DEFAULT 0x00 -#define ICH5R_GPIO_INV_OFF 0x40 -#define ICH5R_GPIO_INV_ON 0x80 - - /* GPIO use select */ - unsigned char gpio[64]; - unsigned int pirq_a_d; - unsigned int pirq_e_h; -}; - -#endif /* I82801EX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c deleted file mode 100644 index cdf1f62..0000000 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ /dev/null @@ -1,130 +0,0 @@ -#include "smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - print_spew("SMBus controller enabled\n"); - - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); - /* Set smbus enable */ - pci_write_config8(dev, 0x40, 1); - /* Set smbus iospace enable */ - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - pci_write_config8(dev, 0x11, 4); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -#ifdef UNUSED_CODE -static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return; - } - - print_debug("Unimplemented smbus_write_byte() called.\n"); - -#if 0 - /* setup transaction */ - /* disable interrupts */ - outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), - SMBUS_IO_BASE + SMBGCTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR); - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - - /* clear the data word...*/ - outw(val, SMBUS_IO_BASE + SMBHSTDAT); - - /* start the command */ - outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(SMBUS_IO_BASE); -#endif - return; -} - -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ - unsigned char byte; - unsigned char stat; - int i; - - /* chear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return -2; - } - - /* setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for(stat=0;(stat&0x40)==0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* set the command address */ - outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - - /* set the block length */ - outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - - /* try sending out the first byte of data here */ - byte=(data1>>(0))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for(i=0;i<length;i++) { - - /* poll for transaction completion */ - if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { - return -3; - } - - /* load the next byte */ - if(i>3) - byte=(data2>>(i%4))&0x0ff; - else - byte=(data1>>(i))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - - /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -} -#endif diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c deleted file mode 100644 index 28164c5..0000000 --- a/src/southbridge/intel/i82801ex/ehci.c +++ /dev/null @@ -1,51 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include "i82801ex.h" - -static void ehci_init(struct device *dev) -{ - uint32_t cmd; - - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_MASTER); - - printk(BIOS_DEBUG, "done.\n"); -} - -static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - uint8_t access_cntl; - access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &ehci_set_subsystem, -}; -static struct device_operations ehci_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_EHCI, -}; diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c deleted file mode 100644 index fc41645..0000000 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "i82801ex.h" - -void i82801ex_enable(device_t dev) -{ - device_t lpc_dev; - unsigned index = 0; - uint16_t reg_old, reg; - - /* See if we are behind the i82801ex pci bridge */ - lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { - index = dev->path.pci.devfn & 7; - } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { - index = (dev->path.pci.devfn & 7) +8; - } - if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) { - return; - } - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | - (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { - return; - } - } - - reg = reg_old = pci_read_config16(lpc_dev, 0xf2); - reg &= ~(1 << index); - if (!dev->enabled) { - reg |= (1 << index); - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, 0xf2, reg); - } - -} - -struct chip_operations southbridge_intel_i82801ex_ops = { - CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge") - .enable_dev = i82801ex_enable, -}; diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h deleted file mode 100644 index 3c7321a..0000000 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef I82801EX_H -#define I82801EX_H - -#include "chip.h" - -extern void i82801ex_enable(device_t dev); - -#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 - -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define GPIO_EN (1 << 4) - -#endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c deleted file mode 100644 index 542c594..0000000 --- a/src/southbridge/intel/i82801ex/ide.c +++ /dev/null @@ -1,42 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void ide_init(struct device *dev) -{ - /* Enable IDE devices and timmings */ - pci_write_config16(dev, 0x40, 0x0a307); // IDE0 - pci_write_config16(dev, 0x42, 0x0a307); // IDE1 - pci_write_config8(dev, 0x48, 0x05); - pci_write_config16(dev, 0x4a, 0x0101); - pci_write_config16(dev, 0x54, 0x5055); - printk(BIOS_DEBUG, "IDE Enabled\n"); -} - -static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = i82801ex_ide_set_subsystem, -}; -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_IDE, -}; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c deleted file mode 100644 index 1823e65..0000000 --- a/src/southbridge/intel/i82801ex/lpc.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * (C) 2004 Linux Networx - */ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include "i82801ex.h" - - -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -/** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801ex_enable_acpi(struct device *dev) -{ - u8 gpio_cntl; - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, GPIO_CNTL); - gpio_cntl |= GPIO_EN; - pci_write_config8(dev, GPIO_CNTL, gpio_cntl); -} - -/** - * Set miscellanous static southbridge features. - * - * @param dev PCI device with I/O APIC configuration registers - */ -static void i82801ex_general_cntl(struct device *dev) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ - reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ - pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - - reg32 = pci_read_config32(dev, GEN_STS); - reg32 |= (1<<1); - pci_write_config32(dev, GEN_STS, reg32); - -} - -#define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) -{ - /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); -} - -#define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) -{ - /* Set PCI DMA CFG to lpc I/F DMA */ - pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); -} - -#define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) -{ - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); -} - -typedef struct southbridge_intel_i82801ex_config config_t; - -static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_use_sel, gpio_use_sel2; - int i; - - gpio_use_sel = 0x1A003180; - gpio_use_sel2 = 0x00000007; - for(i = 0; i < 64; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) { - case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break; - case ICH5R_GPIO_USE_AS_GPIO: val = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_use_sel &= ~( 1 << i); - gpio_use_sel |= (val << i); - } else { - gpio_use_sel2 &= ~( 1 << (i - 32)); - gpio_use_sel2 |= (val << (i - 32)); - } - } - outl(gpio_use_sel, res->base + 0x00); - outl(gpio_use_sel2, res->base + 0x30); -} - -static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_io_sel, gpio_io_sel2; - int i; - - gpio_io_sel = 0x0000ffff; - gpio_io_sel2 = 0x00000300; - for(i = 0; i < 64; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { - case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; - case ICH5R_GPIO_SEL_INPUT: val = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_io_sel &= ~( 1 << i); - gpio_io_sel |= (val << i); - } else { - gpio_io_sel2 &= ~( 1 << (i - 32)); - gpio_io_sel2 |= (val << (i - 32)); - } - } - outl(gpio_io_sel, res->base + 0x04); - outl(gpio_io_sel2, res->base + 0x34); -} - -static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_lvl, gpio_lvl2; - uint32_t gpio_blink; - int i; - - gpio_lvl = 0x1b3f0000; - gpio_blink = 0x00040000; - gpio_lvl2 = 0x00030207; - for(i = 0; i < 64; i++) { - int val, blink; - switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) { - case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; - case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; - case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_lvl &= ~( 1 << i); - gpio_blink &= ~( 1 << i); - gpio_lvl |= ( val << i); - gpio_blink |= (blink << i); - } else { - gpio_lvl2 &= ~( 1 << (i - 32)); - gpio_lvl2 |= (val << (i - 32)); - } - } - outl(gpio_lvl, res->base + 0x0c); - outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); -} - -static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_inv; - int i; - - gpio_inv = 0x00000000; - for(i = 0; i < 32; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { - case ICH5R_GPIO_INV_OFF: val = 0; break; - case ICH5R_GPIO_INV_ON: val = 1; break; - default: - continue; - } - gpio_inv &= ~( 1 << i); - gpio_inv |= (val << i); - } - outl(gpio_inv, res->base + 0x2c); -} - -static void i82801ex_pirq_init(device_t dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if(config->pirq_a_d) { - pci_write_config32(dev, 0x60, config->pirq_a_d); - } - if(config->pirq_e_h) { - pci_write_config32(dev, 0x68, config->pirq_e_h); - } -} - - -static void i82801ex_gpio_init(device_t dev) -{ - struct resource *res; - config_t *config; - - /* Skip if I don't have any configuration */ - if (!dev->chip_info) { - return; - } - /* The programmer is responsible for ensuring - * a valid gpio configuration. - */ - - /* Get the chip configuration */ - config = dev->chip_info; - /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BASE); - if (!res) { - return; - } - - /* Set the use selects */ - set_i82801ex_gpio_use_sel(dev, res, config); - - /* Set the IO direction */ - set_i82801ex_gpio_direction(dev, res, config); - - /* Setup the input inverters */ - set_i82801ex_gpio_inv(dev, res, config); - - /* Set the value on the GPIO output pins */ - set_i82801ex_gpio_level(dev, res, config); - -} - -static void enable_hpet(struct device *dev) -{ - const unsigned long hpet_address = 0xfed00000; - - uint32_t dword; - uint32_t code = (0 & 0x3); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (1 << 17); /* enable hpet */ - - /* Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - - dword &= ~(3 << 15); /* clear it */ - dword |= (code<<15); - pci_write_config32(dev, GEN_CNTL, dword); - - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) ); -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - - i82801ex_general_cntl(dev); - - /* IO APIC initialization. */ - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. - - i82801ex_enable_serial_irqs(dev); - - i82801ex_pci_dma_cfg(dev); - - i82801ex_enable_lpc(dev); - - /* Clear SATA to non raid */ - pci_write_config8(dev, 0xae, 0x00); - - get_option(&pwr_on, "power_on_after_fail"); - byte = pci_read_config8(dev, 0xa4); - byte &= 0xfe; - if (!pwr_on) { - byte |= 1; - } - pci_write_config8(dev, 0xa4, byte); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); - - /* Set up the PIRQ */ - i82801ex_pirq_init(dev); - - /* Set the state of the gpio lines */ - i82801ex_gpio_init(dev); - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Disable IDE (needed when sata is enabled) */ - pci_write_config8(dev, 0xf2, 0x60); - - enable_hpet(dev); -} - -static void i82801ex_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add the ACPI BAR */ - res = pci_get_resource(dev, PMBASE); - - /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BASE); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void i82801ex_lpc_enable_resources(device_t dev) -{ - /* Enable the normal PCI resources. */ - pci_dev_enable_resources(dev); - - /* Enable ACPI and GPIO BARs. */ - i82801ex_enable_acpi(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations lpc_ops = { - .read_resources = i82801ex_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i82801ex_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_LPC, -}; diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c deleted file mode 100644 index f1c8183..0000000 --- a/src/southbridge/intel/i82801ex/pci.c +++ /dev/null @@ -1,44 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void pci_init(struct device *dev) -{ - uint16_t word; - - /* Clear system errors */ - word = pci_read_config16(dev, 0x06); - word |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, word); - -#if 0 - /* System error enable */ - uint32_t dword; - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* SERR# Enable */ - dword |= (1<<6); /* Parity Error Response */ - pci_write_config32(dev, 0x04, dword); -#endif - - word = pci_read_config16(dev, 0x1e); - word |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, word); -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_PCI, -}; diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c deleted file mode 100644 index 9936892..0000000 --- a/src/southbridge/intel/i82801ex/reset.c +++ /dev/null @@ -1,8 +0,0 @@ -#include <arch/io.h> -#include <reset.h> - -void hard_reset(void) -{ - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c deleted file mode 100644 index b3d8f37..0000000 --- a/src/southbridge/intel/i82801ex/sata.c +++ /dev/null @@ -1,59 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void sata_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SATA init\n"); - /* SATA configuration */ - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x09, 0x8f); - - /* Set timmings */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); - - /* Sync DMA */ - pci_write_config16(dev, 0x48, 0x000f); - pci_write_config16(dev, 0x4a, 0x1111); - - /* 66 mhz */ - pci_write_config16(dev, 0x54, 0xf00f); - - /* Combine ide - sata configuration */ - pci_write_config8(dev, 0x90, 0x0); - - /* port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x33); - - /* initialize SATA */ - pci_write_config16(dev, 0xa0, 0x0018); - pci_write_config32(dev, 0xa4, 0x00000264); - pci_write_config16(dev, 0xa0, 0x0040); - pci_write_config32(dev, 0xa4, 0x00220043); - -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_SATA, -}; - -static const struct pci_driver sata_driver_nr __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_SATA, -}; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c deleted file mode 100644 index fe49e11..0000000 --- a/src/southbridge/intel/i82801ex/smbus.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <device/device.h> -#include <device/path.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus.h> -#include <arch/io.h> -#include "i82801ex.h" -#include "smbus.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static struct pci_operations lops_pci = { - /* The subsystem id follows the ide controller */ - .set_subsystem = 0, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_SMB, -}; diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h deleted file mode 100644 index b166797..0000000 --- a/src/southbridge/intel/i82801ex/smbus.h +++ /dev/null @@ -1,104 +0,0 @@ -#include <device/smbus_def.h> - -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (100*1000*10) - - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while(byte & 1); - return loops?0:-1; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); - return loops?0:-1; -} - -static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte&(1<<7)) == 0); - return loops?0:-1; -} - -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* setup transaction */ - /* disable interrupts */ - outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, smbus_io_base + SMBHSTDAT0); - - /* start the command */ - outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - global_status_register &= ~(3 << 5); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c deleted file mode 100644 index c9cf82e..0000000 --- a/src/southbridge/intel/i82801ex/uhci.c +++ /dev/null @@ -1,55 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void uhci_init(struct device *dev) -{ - uint32_t cmd; - -#if 1 - printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_MASTER); - - - printk(BIOS_DEBUG, "done.\n"); -#endif - -} - -static struct pci_operations lops_pci = { - /* The subsystem id follows the ide controller */ - .set_subsystem = 0, -}; - -static struct device_operations uhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB1, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB2, -}; - -static const struct pci_driver usb3_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB3, -}; diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c deleted file mode 100644 index 28e1f5e..0000000 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ /dev/null @@ -1,28 +0,0 @@ -#include <console/console.h> -#include <watchdog.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> - -void watchdog_off(void) -{ - device_t dev; - unsigned long value,base; - - /* turn off the ICH5 watchdog */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - /* Disable the watchdog timer */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); -}