Name of user not set #1002476 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN ......................................................................
Patch Set 4:
(4 comments)
It's done.
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG@7 PS2, Line 7: src: Kconfig: Update config for default path
This is too vague. How about: […]
Ack
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... File src/cpu/intel/fsp_model_406dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... PS2, Line 62:
This will likely break things for users of this CPU. […]
I take it back this time.
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... PS2, Line 104:
Please add the microcode headers to 3rdparty/blobs/soc/intel/baytrail/ instead of removing this opti […]
Though I have known to this path doesn't point it out before as these headers doesn't work for me (may be I'm not lucky) on minnow board max and as binary is also present and already included as an alternative. As the files present in 3rdparty/blobs/soc/intel/baytrail/ are not exact same headers, I am leaving it as is.
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... PS2, Line 51:
This should probably be left alone until the mainboards which use Rangeley each have a default descr […]
Done