[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Select CPU_INTEL_COMMON

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45037 )

Change subject: soc/intel/icelake: Select CPU_INTEL_COMMON
......................................................................

soc/intel/icelake: Select CPU_INTEL_COMMON

This is necessary to show the prompt for ENABLE_VMX, whose value is
written to a FSP UPD. Otherwise, it is always set to zero.

Drop CPU_INTEL_COMMON_SMM since CPU_INTEL_COMMON enables it by default.

Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom and ENABLE_VMX not selected, the resulting binary remains
identical. Selecting ENABLE_VMX changes a single byte from 0x00 to 0x01.

Change-Id: I9b0ca209b60f9804b8f56497046eff96da01cb5c
Signed-off-by: Angel Pons 
---
M src/soc/intel/icelake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45037/1

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 1230675..2aeb6d6 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -15,6 +15,7 @@
    select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
    select BOOT_DEVICE_SUPPORTS_WRITES
    select CACHE_MRC_SETTINGS
+	select CPU_INTEL_COMMON
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
    select FSP_M_XIP
    select GENERIC_GPIO_LIB
@@ -34,7 +35,6 @@
    select FSP_PEIM_TO_PEIM_INTERFACE
    select REG_SCRIPT
    select PMC_GLOBAL_RESET_ENABLE_LOCK
-	select CPU_INTEL_COMMON_SMM
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK