Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195
-gerrit
commit 589d7c83121501ebd926c36ddf08f63d0ac058cc Author: Martin Roth gaumless@gmail.com Date: Sun Jan 11 14:58:47 2015 -0700
FSP platforms: Clear area in CAR for cbmem
cbmem requires that the memory at DCACHE_RAM_BASE be cleared or it does not get used.
This patch clears CAR used by cbmem. Most of the CAR implementations clear the entire area when setting up the CAR area. The FSP loads the entire are with a pattern instead.
Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth gaumless@gmail.com --- src/arch/x86/include/arch/early_variables.h | 1 + src/cpu/x86/car.c | 7 +++++++ src/mainboard/intel/cougar_canyon2/romstage.c | 4 ++++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 +++ src/southbridge/intel/fsp_rangeley/romstage.c | 4 ++++ 5 files changed, 19 insertions(+)
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..1a11b93 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -61,6 +61,7 @@ static inline void *car_get_var_ptr(void *var) { return var; } #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) /* Migrate the CAR variables to memory. */ void car_migrate_variables(void); +void clear_car_data_area(void); #else static inline void car_migrate_variables(void) { } #endif diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..81230bd 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -105,6 +105,13 @@ void *car_sync_var_ptr(void *var) return mig_var; }
+void clear_car_data_area(void) +{ + size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + + memset(&_car_data_start[0], 0, car_data_size); +} + static void do_car_migrate_variables(void) { void *migrated_base; diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 72832ea..6879e14 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -24,6 +24,7 @@ #include <string.h> #include <lib.h> #include <timestamp.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -180,6 +181,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) u32 pm1_cnt; u16 pm1_sts;
+ /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); + post_code(0x40);
#if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b0b8133..9e86dc3 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <arch/cpu.h> #include <lib.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> @@ -158,6 +159,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0;
+ /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); post_code(0x40);
program_base_addresses(); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..30ac56b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -22,6 +22,7 @@ #include <string.h> #include <lib.h> #include <timestamp.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -44,6 +45,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
+ /* Clear CAR Memory for CBMEM */ + clear_car_data_area(); + /* * Do not use the Serial Console before it is setup. * This causes the I/O to clog and a side effect is