[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

[huayang duan (Code Review)]

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

the delay cell result should using the ddr clock pll rate for compute,
should not div 2 more.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 1dc1ca5..c61e237 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -1588,18 +1588,24 @@
    struct per_byte_dly center_dly[DQS_NUMBER];
    u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];

+
+	/*
+	* The clock rate should be (data rate/2 - 4),
+	* and the 4MHz is introduced to reduce interference from
+	* RF peripherals like modem, WiFi, BlueTooth.
+	*/
    switch (freq_group) {
    case LP4X_DDR1600:
-		clock_rate = 800;
+		clock_rate = 796;
    	break;
    case LP4X_DDR2400:
-		clock_rate = 1200;
+		clock_rate = 1196;
    	break;
    case LP4X_DDR3200:
-		clock_rate = 1600;
+		clock_rate = 1596;
    	break;
    case LP4X_DDR3600:
-		clock_rate = 1866;
+		clock_rate = 1792;
    	break;
    default:
    	die("Invalid DDR frequency group %u\n", freq_group);
@@ -1612,7 +1618,7 @@
    	use_delay_cell = 0;

if (fast_calib && bypass_tx) {
-		dramc_dbg("bypass TX\n");
+		dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate);
    	for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
    		center_dly[byte].min_center = params->tx_center_min[chn][rank][byte];
    		center_dly[byte].max_center = params->tx_center_max[chn][rank][byte];
@@ -1645,8 +1651,10 @@
    			tune_diff = vref_dly[index].win_center -
    				center_dly[byte].min_center;
    			dq_delay_cell[index] = ((tune_diff * 100000000) /
-					(clock_rate / 2 * 64)) / dly_cell_unit;
+					(clock_rate * 64)) / dly_cell_unit;
    			byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4));
+				dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n",
+					index, dq_delay_cell[index], tune_diff);
    		}
    	}
    }