[coreboot-gerrit] [M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size

[Nico Huber (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Michał Żygowski, Patrick Rudolph.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email )

Change subject: device/pciexp_device.c: Fix setting Max Payload Size
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Patch Set 11:

(1 comment)

Patchset:

PS11: 
So I looked into the spec again and the reasons why we handled this (badly)
in coreboot in the first place. This seems to be much more of a thing to be
configured by the OS. It was only introduced into coreboot as a workaround
for a broken FSP: https://ticket.coreboot.org/issues/218

So maybe before we go deeper down this rabbit hole, should we test if dis-
abling the code would allow the OS to do its job properly? Or alternatively,
to fix any potential damage done by FSP, simply reset all settings to the
default 128B.